HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 178

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6.6
The time from generation of an interrupt request until interrupt exception processing is performed
and fetching of the first instruction of the exception handler is started (the interrupt response time)
is shown in table 6.7. Figure 6.4 shows an example of pipeline operation when an IRL interrupt is
accepted. When SR.BL is 1, interrupt exception processing is masked, and is kept waiting until
completion of an instruction that clears BL to 0.
The response time is represented by the clock number of I . Depending on the P phase when an
interrupt is occurred, one clock period of P may vary from the contents of this table.
Table 6.7
Rev. 4.00, 03/04, page 132 of 660
Item
Time for priority
decision and SR
mask bit
comparison
Wait time until
end of sequence
being executed
by CPU
Time from
interrupt
exception
processing (save
of SR and PC)
until fetch of first
instruction of
exception service
routine is started
Interrupt Response Time
Interrupt Response Time
NMI
0.5 × Icyc
+ 1.5 × Bcyc
X ( 0) × Icyc X ( 0) × Icyc X ( 0) × Icyc X ( 0) × Icyc Interrupt exception processing is
5 × Icyc
IRQ
1.5 × Icyc
+ 0.5 × Bcyc
+ 2 × Pcyc*
5 × Icyc
Number of States
2
IRL
0.5 × Icyc
+ 0.5 × Bcyc
+ 3.5 × Pcyc
5 × Icyc
Peripheral
Modules
0.5 × Icyc
+ 1.5 × Pcyc*
0.5 × Icyc
+ 3 × Pcyc*
5 × Icyc
4
3
Notes
kept waiting until the executing
instruction ends. If the number of
instruction execution states is S*
the maximum wait time is: X = S –
1. However, if BL is set to 1 by
instruction execution or by an
exception, interrupt exception
processing is deferred until
completion of an instruction that
clears BL to 0. If the following
instruction masks interrupt
exception processing, the
processing may be further
deferred.
1
,