HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 335

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 9.8
If the indirect address is on, data stored in the address set in SAR_0 to SAR_3 is not used as
transfer source data. In the indirect address, after the value stored in the address set in SAR_0 to
SAR_3 is read, that read value is used as an address again, and the value stored in that address is
read and stored in the corresponding address set in DAR_0 to DAR_3.
In the example shown in table 9.3, when an SCIF transfer request is generated, the DMAC reads
the value in address H'00400000 set in SAR_3. Since the value H'00450000 is stored in that
address, the DMAC reads the value H'00450000. Next, the DMAC uses that read value as an
address again, and reads the value H'55 stored in that address. Then, the DMAC writes the value
H'55 to address H'04000156 set in DAR_3; this completes one indirect address transfer.
In the indirect address, when data is read first from the address set in SAR_3, the data transfer size
is always longword regardless of the settings of the TS0 and the TS1 bits that specify the transfer
data size. However, whether the transfer source address is fixed, incremented, or decremented is
specified according to the SM0 and the SM1 bits. Therefore, in this example, though the transfer
data size is specified as byte, the value in SAR_3 is H'00400004 when one transfer ends. Write
operation is the same as that in the normal dual address transfer.
Transfer Conditions
Transfer source: external memory
Value stored in address H'00400000
Value stored in address H'04500000
Transfer destination: On-chip SCIF TDR2
Number of transfers: 10
Transfer source address: incremented
Transfer destination address: fixed
Transfer request source: SCIF (TXI2)
Bus mode: cycle steal
Transfer unit: byte
Channel priority order: 0 > 1 > 2 > 3
No interrupt request generated at end of transfer
Transfer Conditions and Register Settings for Transfer between External
Memory and SCIF Transmitter
SAR_3
—
DAR_3
DMAOR
Register
—
DMATCR_3 H'0000000A
CHCR_3
Rev. 4.00, 03/04, page 289 of 660
Setting
H'00400000
H'00450000
H'55
H'04000156
H'00011C01
H'0001