HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 370

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12.5.3
The TMU produces underflow interrupts for each channel. When the interrupt request flag and
interrupt enable bit are both set to 1, the interrupt is requested. Codes are set in the exception event
register (INTEVT, INTEVT2) for these interrupts and interrupt processing occurs according to the
codes.
The relative priorities of channels can be changed using the interrupt controller (see section 4,
Exception Processing, and section 6, Interrupt Controller (INTC)). Table 12.2 lists TMU interrupt
sources.
Table 12.2 TMU Interrupt Sources
12.6
12.6.1
Synchronization processing is not performed for timer counting during register writes. When
writing to registers, always clear the appropriate start bits for the channel (STR2 to STR0) in the
timer start register (TSTR) to halt timer counting.
12.6.2
Synchronization processing is performed for timer counting during register reads. When timer
counting and register read processing are performed simultaneously, the register value before
TCNT counting down (with synchronization processing) is read.
Rev. 4.00, 03/04, page 324 of 660
Channel
0
1
2
Interrupt Sources and Priorities
Usage Note
Writing to Registers
Reading Registers
Interrupt Source
TUNI0
TUNI1
TUNI2
TICPI2
Description
Underflow interrupt 0
Underflow interrupt 1
Underflow interrupt 2
Input capture interrupt 2
Priority
High
Low