HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 138

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Rev. 4.00, 03/04, page 92 of 660
Initial page write exception
The PC and SR of the instruction that generated the exception are saved to the SPC and SSR,
respectively. H'080 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a
branch occurs in PC
TLB protection exception
The PC and SR of the instruction that generated the exception are saved to the SPC and SSR,
respectively. If the exception occurred during a read, H'0A0 is set in EXPEVT; if the exception
occurred during a write, H'0C0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1
and a branch occurs to PC = VBR + H'0100.
Address error
A. Instruction fetch from odd address (4n + 1, 4n + 3)
B. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)
C. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2,
D. Virtual space accessed in user mode in the area H'80000000 to H'FFFFFFFF.
Conditions: A hit occurred to the TLB for a store access, but D
writes to the page registered by the load.)
Operations: The virtual address (32 bits) that caused the exception is set in TEA and the
corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH
indicates the ASID at the time the exception occurred. The way that generated the
exception is set in the RC bit in MMUCR.
Conditions: When a hit access violates the TLB protection information (PR bits) shown
below:
Operations: The virtual address (32 bits) that caused the exception is set in TEA and the
corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH
indicates the ASID at the time the exception occurred. The way that generated the
exception is set in the RC bits in MMUCR.
Conditions: When corresponded to the following items.
4n + 3)
PR
00
01
10
11
Privileged mode
Only read enabled
Read/write enabled
Only read enabled
Read/write enabled
VBR + H'0100.
User mode
No access
No access
Only read enabled
Read/write enabled
0. (This occurs for initial