HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 190
![no-image](/images/no-image-200.jpg)
HD6417706
Manufacturer Part Number
HD6417706
Description
Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6417706.pdf
(709 pages)
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- Current page: 190 of 709
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Rev. 4.00, 03/04, page 144 of 660
Bit
12
11
10
9, 8
7
6
5, 4
Bit Name
SCMFDB
PCTE
PCBA
—
DBEB
PCBB
—
Initial Value R/W
0
0
0
All 0
0
0
All 0
R/W
R/W
R/W
R
R/W
R/W
R
When the on-chip DMAC bus cycle condition in the
break conditions set for channel B is satisfied, this
flag is set to 1 (not cleared to 0). In order to clear this
flag, write 0 into this bit.
0: The DMAC cycle condition for channel B does not
1: The DMAC cycle condition for channel B matches
Enables PC trace.
0: Disables PC trace
1: Enables PC trace
Selects the break timing of the instruction fetch cycle
for channel A as before or after instruction execution.
0: PC break of channel A is set before instruction
1: PC break of channel A is set after instruction
These bits are always read as 0. The write value
should always be 0.
Selects whether or not the data bus condition is
included in the break condition of channel B.
0: No data bus condition is included in the condition of
1: The data bus condition is included in the condition
Selects the break timing of the instruction fetch cycle
for channel B as before or after instruction execution.
0: PC break of channel B is set before instruction
1: PC break of channel B is set after instruction
These bits are always read as 0. The write value
should always be 0.
Description
DMAC Condition Match Flag B
PC Trace Enable
PC Break Select A (PCBA)
Reserved
Data Break Enable B
PC Break Select B
Reserved
match
execution
execution
channel B
of channel B
execution
execution
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