HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 441

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Transmitting and Receiving Serial Data Simultaneously (Clock Synchronous Mode): Figure
14.23 shows a sample flowchart for transmitting and receiving serial data simultaneously.
Simultaneous transmission and reception of serial data should be carried out in the following
procedure after setting the SCI in a transmission/reception-enabled state.
Note: In switching from transmitting or receiving to simultaneous transmitting and receiving, clear both
Figure 14.23 Sample Flowchart for Serial Data Transmitting/Receiving
TE and RE to 0, then set both TE and RE to 1.
No
No
No
and clear RDRF bit in SCSSR to 0
Write transmission data to SCTDR
and clear TDRE bit in SCSSR to 0
Read receive data of SCRDR
Start transmission/reception
End transmission/reception
Read ORER bit in SCSSR
Read TDRE bit in SCSSR
Read RDRF bit in SCSSR
transmitted/received?
Clear TE and RE bits
in SCSCR to 0
ORER = 1?
RDRF = 1?
TDRE = 1?
All data
Yes
No
Yes
Yes
Yes
1.
2.
3.
4.
SCI status check and transmit data write: Read the
SCSSR, check that the TDRE bit is 1, then write
transmit data in the SCTDR and clear TDRE to
0. The TXI interrupt can also be used to determine
if the TDRE bit has changed from 0 to 1.
Receive error processing: If a receive error occurs,
read the ORER bit in SCSSR to identify the error.
After executing the necessary error processing,
clear ORER to 0. Transmitting/receiving cannot
resume if ORER remains set to 1.
SCI status check and receive data read: Read the
SCSSR, check that RDRF is set to 1, then read
receive data from the SCRDR and clear RDRF
to 0. The RXI interrupt can also be used to
determine if the RDRF bit has changed from 0 to 1.
To continue transmitting and receiving serial data:
Read the RDRF bit and SCRDR, and clear RDRF
to 0 before the frame MSB (bit 7) of the current
frame is received. Also read the TDRE bit to check
whether it is safe to write (if it reads 1); if so, write
data in SCTDR, then clear TDRE to 0 before the
MSB (bit 7) of the current frame is transmitted.
Error processing
Rev. 4.00, 03/04, page 395 of 660