HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 294

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Rev. 4.00, 03/04, page 248 of 660
Bit
20
19
18
17
Bit Name
DI
RO
RL
AM
Initial Value R/W
0
0
0
0
(R/W)*
(R/W)*
(R/W)*
(R/W)*
2
2
2
2
Description
Direct/Indirect Selection
DI selects direct address mode or indirect address
mode in channel 3.
This bit is only valid in CHCR_3 and is not used in
CHCR_0 to CHCR_2. Writing to this bit is invalid in
CHCR_0 to CHCR_2; 0 is read if this bit is read.
When using 16-byte transfer, direct address mode
must be specified. Operation is not guaranteed if
indirect address mode is specified.
0: Direct address mode
1: Indirect address mode
Source Address Reload
RO selects whether the source address initial value
is reloaded in channel 2.
This bit is only valid in CHCR_2 and is not used in
CHCR_0 to CHCR_1, or CHCR_3. Writing to this bit
is invalid in CHCR_0, CHCR_1, and CHCR_3; 0 is
read if this bit is read. When using 16-byte transfer,
this bit must be cleared to 0, specifying non-
reloading. Operation is not guaranteed if reloading is
specified.
0: A source address is not reloaded
1: A source address is reloaded
Request Check Level
RL specifies the DRAK (acknowledge of DREQ)
signal output is high active or low active.
This bit is only valid in CHCR_0 and CHCR_1.
Writing to this bit is invalid in CHCR_2 and CHCR_3;
0 is read if this bit is read.
0: Low-active output of DRAK
1: High-active output of DRAK
Acknowledge Mode
AM specifies whether DACK is output in data read
cycle or in data write cycle in dual address mode.
This bit is only valid in CHCR_0 and CHCR_1.
Writing to this bit is invalid in CHCR_2 and CHCR_3;
0 is read if this bit is read.
0: DACK output in read cycle
1: DACK output in write cycle