HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 34

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 6.4 Example of Pipeline Operations when IRL Interrupt is Accepted ............................ 134
Section 7 User Break Controller
Figure 7.1 Block Diagram of User Break Controller.................................................................. 136
Section 8 Bus State Controller (BSC)
Figure 8.1 BSC Functional Block Diagram................................................................................ 160
Figure 8.2 Corresponding to Logical Address Space and Physical Address Space.................... 163
Figure 8.3 Physical Space Allocation ......................................................................................... 164
Figure 8.4 PCMCIA Space Allocation ....................................................................................... 166
Figure 8.5 Basic Timing of Basic Interface ................................................................................ 200
Figure 8.6 Example of 32-Bit Data-Width Static RAM Connection .......................................... 201
Figure 8.7 Example of 16-Bit Data-Width Static RAM Connection .......................................... 202
Figure 8.8 Example of 8-Bit Data-Width Static RAM Connection ............................................ 202
Figure 8.9 Basic Interface Wait Timing (Software Wait Only) .................................................. 203
Figure 8.10 Basic Interface Wait State Timing
(Wait State Insertion by WAIT Signal WAITSEL = 1).......................................... 204
Figure 8.11 Example of 64-Mbit Synchronous DRAM Connection (32-Bit Bus Width)........... 206
Figure 8.12 Example of 64-Mbit Synchronous DRAM (16-Bit Bus Width) .............................. 207
Figure 8.13 Basic Timing for Synchronous DRAM Burst Read ................................................ 210
Figure 8.14 Synchronous DRAM Burst Read Wait Specification Timing ................................. 211
Figure 8.15 Basic Timing for Synchronous DRAM Single Read............................................... 212
Figure 8.16 Basic Timing for Synchronous DRAM Burst Write ............................................... 213
Figure 8.17 Basic Timing for Synchronous DRAM Single Write.............................................. 214
Figure 8.18 Burst Read Timing (No Precharge) ......................................................................... 216
Figure 8.19 Burst Read Timing (Same Row Address) ............................................................... 217
Figure 8.20 Burst Read Timing (Different Row Addresses) ...................................................... 218
Figure 8.21 Burst Write Timing (No Precharge) ........................................................................ 219
Figure 8.22 Burst Write Timing (Same Row Address)............................................................... 220
Figure 8.23 Burst Write Timing (Different Row Addresses) ..................................................... 221
Figure 8.24 Auto-Refresh Operation .......................................................................................... 222
Figure 8.25 Synchronous DRAM Auto-Refresh Timing............................................................ 223
Figure 8.26 Synchronous DRAM Self-Refresh Timing ............................................................. 224
Figure 8.27 Synchronous DRAM Mode Write Timing .............................................................. 226
Figure 8.28 Burst ROM Wait Access Timing............................................................................. 228
Figure 8.29 Burst ROM Basic Access Timing ........................................................................... 229
Figure 8.30 PCMCIA Space Allocation ..................................................................................... 230
Figure 8.31 Example of PCMCIA Interface ............................................................................... 231
Figure 8.32 Basic Timing for PCMCIA Memory Card Interface ............................................... 232
Figure 8.33 Wait Timing for PCMCIA Memory Card Interface ................................................ 233
Figure 8.34 Basic Timing for PCMCIA Memory Card Interface Burst Access ......................... 234
Figure 8.35 Wait Timing for PCMCIA Memory Card Interface Burst Access .......................... 235
Figure 8.36 Basic Timing for PCMCIA I/O Card Interface ....................................................... 236
Figure 8.37 Wait Timing for PCMCIA I/O Card Interface ........................................................ 237
Rev. 4.00, 03/04, page xxxiv of xlvi