HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 25

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Direct Memory Access Controller (DMAC) .................................... 243
9.1
9.2
9.3
9.4
9.5
9.6
9.7
Section 10 Clock Pulse Generator (CPG)......................................................... 291
10.1 Feature............................................................................................................................... 291
10.2 Input/Output Pin................................................................................................................ 294
10.3 Clock Operating Modes .................................................................................................... 294
10.4 Register Description.......................................................................................................... 298
10.5 Operation........................................................................................................................... 300
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.5.8
8.5.9
Feature............................................................................................................................... 243
Input/Output Pin................................................................................................................ 245
Register Description.......................................................................................................... 245
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
Operation........................................................................................................................... 255
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
9.4.7
Compare Match Timer (CMT).......................................................................................... 282
9.5.1
9.5.2
9.5.3
Examples of Use ............................................................................................................... 287
9.6.1
9.6.2
Cautions ............................................................................................................................ 290
10.4.1 Frequency Control Register (FRQCR)................................................................. 298
Basic Interface ..................................................................................................... 200
Synchronous DRAM Interface............................................................................. 205
Burst ROM Interface............................................................................................ 227
PCMCIA Interface ............................................................................................... 229
Waits between Access Cycles.............................................................................. 239
Bus Arbitration..................................................................................................... 240
Bus Pull-Up.......................................................................................................... 240
DMA Source Address Registers 0 to 3 (SAR_0 to SAR_3) ................................ 246
DMA Destination Address Registers 0 to 3 (DAR_0 to DAR_3)........................ 246
DMA Transfer Count Registers 0 to 3 (DMATCR_0 to DMATCR_3)............... 247
DMA Channel Control Registers 0 to 3 (CHCR_0 to CHCR_3)......................... 247
DMA Operation Register (DMAOR)................................................................... 253
DMA Transfer Flow............................................................................................. 255
DMA Transfer Requests ...................................................................................... 257
Channel Priority ................................................................................................... 259
DMA Transfer Types ........................................................................................... 262
Number of Bus Cycle States and DREQ Pin Sampling Timing .......................... 274
Source Address Reload Function ......................................................................... 278
DMA Transfer Ending Conditions....................................................................... 280
Feature ................................................................................................................. 282
Register Description............................................................................................. 283
Operation ............................................................................................................. 285
Example of DMA Transfer between A/D Converter and External Memory
(Address Reload on) ............................................................................................ 287
Example of DMA Transfer between External Memory and SCIF Transmitter
(Indirect Address on) ........................................................................................... 288
Rev. 4.00, 03/04, page xxv of xlvi