HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 243

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

8.5.2
Area 0: Area 0 physical addresses A28 to A26 are 000. Addresses A31 to A29 are ignored and the
address range is H'00000000 + H'20000000
n
Ordinary memories such as SRAM, ROM, and burst ROM can be connected to this space. Byte,
word, or longword can be selected as the bus width using external pins MD3 and MD4. When the
area 0 space is accessed, a CS0 signal is asserted. An RD signal that can be used as OE and the
WE0 to WE3 signals for write control are also asserted. The number of bus cycles is selected
between 0 and 10 wait cycles using the A0W2 to A0W0 bits of WCR2. In addition, any number of
waits can be inserted in each bus cycle by means of the external wait pin (WAIT). When the burst
function is used, the bus cycle pitch of the burst cycle is determined within a range of 2 to 10
according to the number of waits.
Area 1: Area 1 physical addresses A28 to A26 are 001. Addresses A31 to A29 are ignored and the
address range is H'04000000 + H'20000000
and n
Area 1 is the area specifically for the internal peripheral modules. The external memories cannot
be connected.
Control registers of peripheral modules shown below are mapped to this area 1. Their addresses
are physical address, to which logical addresses can be mapped with the MMU enabled:
Those registers must be set not to be cached.
Area 2: Area 2 physical addresses A28 to A26 are 010. Addresses A31 to A29 are ignored and the
address range is H'08000000 + H'20000000
and n
Ordinary memories like SRAM and ROM, as well as synchronous DRAM, can be connected to
this space. Byte, word, or longword can be selected as the bus width using the A2SZ1 to A2SZ0
bits of BCR2 for ordinary memory.
When the area 2 space is accessed, a CS2 signal is asserted. When ordinary memories are
connected, an RD signal that can be used as OE and the WE0 to WE3 signals for write control are
also asserted and the number of bus cycles is selected between 0 and 3 wait cycles using the
A2W1 to A2W0 bits of WCR2.
When synchronous DRAM is connected, the RASU, RASL signal, CASU, CASL signal, RD/WR
signal, and byte controls DQMHH, DQMHL, DQMLH, and DQMLL are all asserted and
addresses multiplexed. Control of RASU, RASL, CASU, CASL, data timing, and address
multiplexing is set with MCR.
1 to 6 are the shadow spaces).
1 to 6 are the shadow spaces).
1 to 6 are the shadow spaces).
DMAC, PORT, SCIF, ADC, DAC, INTC (except INTEVT, IPRA, IPRB)
Description of Areas
n – H'03FFFFFF + H'20000000
n to H'07FFFFFF + H'20000000
n to H'0BFFFFFF + H'20000000
Rev. 4.00, 03/04, page 197 of 660
n (n
n (n
n (n
0 to 6 and
0 to 6
0 to 6