HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 412

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

14.3.10 Bit Rate Register (SCBRR)
The bit rate register (SCBRR) is an eight-bit register that, together with the baud rate generator
clock source selected by the CKS1 and CKS0 bits in SCSMR, determines the serial
transmit/receive bit rate.
The CPU can always read and write the SCBRR. The SCBRR is initialized to H'FF by a reset or in
module standby or standby mode. Each channel has independent baud rate generator control, so
different values can be set in two channels.
The SCBRR setting is calculated as follows:
Table 14.2 SCSMR Settings
Find the bit rate error for the asynchronous mode by the following formula:
Rev. 4.00, 03/04, page 366 of 660
n
0
1
2
3
Asynchronous mode: N
Clock synchronous mode: N
B:
N:
P : Operating frequency for peripheral modules (MHz)
n:
Error (%) =
Baud rate generator clock source (n
n, see table 14.2.)
Bit rate (bit/s)
SCBRR setting for baud rate generator (0
(N + 1)
Clock Source
P
P /4
P /16
P /64
P B
B
[P /(64
10
64
6
[P /(8
2
2n-1
2
2n – 1
2
1
2n – 1
CKS1
0
0
1
1
0, 1, 2, 3) (for the clock sources and values of
B)]
100
B)]
N
10
6
255)
10
– 1
6
SCSMR Settings
– 1
CKS0
0
1
0
1