HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 504

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6.
The receive margin in asynchronous mode can therefore be expressed as shown in equation 1.
Equation 1:
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2.
Equation 2:
When D = 0.5 and F = 0:
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Rev. 4.00, 03/04, page 458 of 660
data (RxD2)
Receive Data Sampling Timing and Receive Margin
The SCIF operates on a base clock with a frequency of 16 times the transfer rate. In
reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on
the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The
timing is shown in figure 16.13.
Base clock
Synchro-
sampling
sampling
Receive
nization
M
M = 0.5 –
timing
timing
Data
Figure 16.13 Receive Data Sampling Timing in Asynchronous Mode
(0.5 – 1/(2
46.875
0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5
2N
1
Start bit
8 clocks
– (L – 0.5) F –
16))
16 clocks
100
–7.5 clocks
D – 0.5
N
(1 + F)
+7.5 clocks
100%
D0
D1