HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 163

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6.3.5
Tables 6.3 and 6.4 lists the codes for the interrupt event register (INTEVT and INTEVT2), and the
order of interrupt priority. Each interrupt source is assigned unique code. The start address of the
interrupt service routine is common to each interrupt source. This is why, for instance, the value of
INTEVT or INTEVT2 is used as offset at the start of the interrupt service routine and branched to
identify the interrupt source.
The order of priority of the on-chip peripheral module, IRQ, and PINT interrupts is set within the
priority levels 0 to 15 at will by using the interrupt priority level set to registers A to E (IPRA to
IPRE). The order of priority of the on-chip peripheral module, IRQ, and PINT interrupts is set to
zero by RESET.
When the order of priorities for multiple interrupt sources are set to the same level and such
interrupts are generated at the same time, they are processed according to the default order listed
in tables 6.3 and 6.4.
Table 6.3
Interrupt Source
NMI
H-UDI
IRQ
DMAC
SCIF
(SCI2)
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
DEI0
DEI1
DEI2
DEI3
ERI2
RXI2
BRI2
TXI2
Interrupt Exception Processing and Priority
Interrupt Exception Handling Sources and Priority (IRQ Mode)
INTEVT Code
(INTEVT2 Code)
H'1C0 (H'1C0)
H'5E0 (H'5E0)
H'200 to 3C0* (H'600)
H'200 to 3C0* (H'620)
H'200 to 3C0* (H'640)
H'200 to 3C0* (H'660)
H'200 to 3C0* (H'680)
H'200 to 3C0* (H'6A0)
H'200 to 3C0* (H'800)
H'200 to 3C0* (H'820)
H'200 to 3C0* (H'840)
H'200 to 3C0* (H'860)
H'200 to 3C0* (H'900)
H'200 to 3C0* (H'920)
H'200 to 3C0* (H'940)
H'200 to 3C0* (H'960)
Interrupt
Priority
(Initial Value)
16
15
0 to 15 (0)
0 to 15 (0)
0 to 15 (0)
0 to 15 (0)
0 to 15 (0)
0 to 15 (0)
0 to 15 (0)
0 to 15 (0)
IPR (Bit
Numbers)
—
—
IPRC (3 to 0)
IPRC (7 to 4)
IPRC (11 to 8)
IPRC (15 to 12) —
IPRD (3 to 0)
IPRD (7 to 4)
IPRE (15 to 12)
IPRE (7 to 4)
Rev. 4.00, 03/04, page 117 of 660
Priority
within IPR
Setting Unit
—
—
—
—
—
—
—
High
Low
High
Low
Default
Priority
High
Low