HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 478

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Rev. 4.00, 03/04, page 432 of 660
Bit
7
Bit Name
ER
Initial Value
0
R/W
R/(W)* Receive error
Description
Indicates that a framing error or a parity error,
when receiving data containing parity bits, has
occurred.
0: Receive is in progress, or receive is normally
1: A framing error or a parity error has occurred
ER is set to 1 when the stop bit is 0 after
Notes: 1. Clearing the RE bit to 0 in SCSCR2
[Clearing conditions]
[Setting conditions]
during receiving.
checking whether or not the last stop bit of the
received data is 1 at the end of one-data
receive*, or when the total number of 1's in the
received data and in the parity bit does not
match the even/odd parity specification
specified by the O/E bit of the SCSMR.
completed.*
1. The stop bit is 0 after checking whether
2. The total number of 1's in the received
1. The chip is power-on reset or enters
2. ER is read as 1, then written to with 0.
2. n the stop mode, only the first stop bit
standby mode.
or not the last stop bit of the received
data is 1 at the end of one-data
receive.*
data and in the parity bit does not match
the even/odd parity specification
specified by the O/E bit of the SCSMR2.
does not affect the ER bit, which
retains its previous value. Even if a
receive error occurs, the received
data is transferred to SCFRDR2 and
the receive operation is continued.
Whether or not the data read from
SCRDR2 includes a receive error can
be detected by the FER and PER bits
of SCSSR2.
is checked; the second stop bit is not
checked.
1
2