HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 401

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

14.3.6
The serial control register (SCSCR) operates the SCI transmitter/receiver, selects the serial clock
output in the asynchronous mode, enables/disables interrupt requests, and selects the
transmit/receive clock source. The CPU can always read and write the SCSCR.
Bit
2
1
0
Bit
7
Serial Control Register (SCSCR)
Bit Name
MP
CKS1
CKS0
Bit Name
TIEs
Initial Value
0
0
0
Initial Value
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Multiprocessor Mode
Selects multiprocessor format. When
multiprocessor format is selected, settings of the
PE and O/E bits are ignored. The MP setting is
used available in the asynchronous mode; it is
ignored in the clock synchronous mode. For the
multiprocessor communication function, see
section 14.4.2, Multiprocessor Communication.
0: Multiprocessor function disabled
1: Multiprocessor format selected
Clock Select 1 and 0
These bits select the internal clock source of the
on-chip baud rate generator. Four clock sources
are available. P , P /4, P /16 and P /64. For
further information on the clock source, bit rate
register settings, and baud rate, see section
14.3.10, Bit Rate Register (SCBRR).
00: P
01: P /4
10: P /16
11: P /64
Note: P : Peripheral clock
Description
Transmit Interrupt Enable
Enables or disables the TXI request when the
serial transmit data is transferred from SCTDR to
SCTCR and the TDRE in SCSSR is set to 1.
0: Transmit-data-empty interrupt request (TXI) is
Note: The TXI interrupt request can be cleared by
reading TDRE after it has been set to 1, then
clearing TDRE to 0, or by clearing TIE to 0.
1: Transmit-data-empty interrupt request (TXI) is
disabled
enabled
Rev. 4.00, 03/04, page 355 of 660