HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 467

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

This LSI has single-channel serial communication interface with FIFO (SCIF) that supports
asynchronous serial communication. It also has 16-stage FIFO registers for both transfer and
receive that enables this LSI efficient high-speed continuous communication. Figure 16.1 shows a
diagram of the SCIF, and figures 16.2 to 16.4 show the I/O ports.
16.1
Asynchronous serial communication
Full duplex communication
The transmitting and receiving sections are independent, so the SCI can transmit and receive
simultaneously. Both sections use 16-stage FIFO buffering, so high-speed continuous data
transfer is possible in both the transmit and receive directions.
On-chip baud rate generator with selectable bit rates
Internal or external transmit/receive clock source
From either baud rate generator (internal) or SCK2 pin (external)
Four types of interrupts
Transmit-FIFO-data-empty, break, receive-FIFO-data-full, and receive-error interrupts are
requested independently. The direct memory access controller (DMAC) can be activated to
execute a data transfer by a transmit-FIFO-data-empty or receive-FIFO-data-full interrupt.
When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving
power.
On-chip modem control functions (RTS2 and CTS2)
The quantity of data in the transmit and receive FIFO registers and the number of receive
errors of the receive data in the receive FIFO register can be known.
The time-out error (DR) can be detected in receiving.
Section 16 Serial Communication Interface with FIFO
Serial data communications are performed by start-stop in character units. The SCI can
communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous
communication interface adapter (ACIA), or any other communications chip that employs
a standard asynchronous serial system. There are eight selectable serial data
communication formats.
Data length: Seven or eight bits
Stop bit length: One or two bits
Parity: Even, odd, or none
Receive error detection: Parity and framing errors
Break detection:
Feature
(SCIF)
Rev. 4.00, 03/04, page 421 of 660