HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 503

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

16.5
Note the following when using the SCIF.
1.
2.
3.
4.
5.
The TDFE flag in SCSSR2 is set when the number of transmit data bytes written in the
SCFTDR2 has fallen below the transmit trigger number set by bits TTRG1 and TTRG0 in the
SCFCR2. After TDFE is set, transmit data up to the number of empty bytes in SCFTDR2 can
be written, allowing efficient continuous transmission.
If the number of data bytes written in SCFTDR2 is equal to or less than the transmit trigger
number, the TDFE flag will be set to 1 again after being cleared to 0. TDFE clearing should
therefore be carried out after data more than the specified number of transmit triggers has
been written to SCFTDR2.
The number of transmit data bytes in SCFTDR2 can be found from the upper 8 bits of the
SCFDR2.
The RDF flag in SCSSR2 is set when the number of receive data bytes in the SCFRDR2 has
become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in
SCFCR2. After RDF is set, receive data equivalent to the trigger number can be read from
SCFRDR2, allowing efficient continuous reception.
However, if the number of data bytes in SCFRDR2 is greater than the trigger number, the
RDF flag will be set to 1 again even if it is cleared to 0. The RDF flag should therefore be
cleared to 0 after being read as 1 after all the receive data has been read.
The number of receive data bytes in SCFRDR2 can be found from the lower 8 bits of the
FIFO data count register (SCFDR2).
Break signals can be detected by reading the RxD2 pin directly when a framing error (FER) is
detected. In the break state the input from the RxD2 pin consists of all 0s, so the FER flag is
set and the parity error flag (PER) may also be set. Note that, although transfer of receive
data to SCFRDR2 is halted in the break state, the SCIF receiver continues to operate, so if the
BRK flag is cleared to 0 it will be set to 1 again.
The I/O condition and level of the TxD2 pin are determined by the SCP2DT bit in SCPDR
and bits SCP2MD0 and SCP2MD1 in the SCPCR. This feature can be used to send a break
signal.
To send a break signal during serial transmission, clear the SCP2DT bit to 0 (designating low
level), then set the SCP2MD0 and SCP2MD1 bits to 0 and 1, respectively, and finally clear
the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is
initialized regardless of the current transmission state, and 0 is output from the TxD2 pin.
TEND Flag and TE Bit Processing
The TEND flag is set to 1 during transmission of the stop bit of the last data. Consequently, if
the TE bit is cleared to 0 immediately after setting of the TEND flag has been confirmed, the
stop bit will be in the process of transmission and will not be transmitted normally.
Therefore, the TE bit should not be cleared to 0 for at least 0.5 serial clock cycles (or 1.5
cycles if two stop bits are used) after setting of the TEND flag setting is confirmed.
SCFTDR2 Writing and the TDFE Flag
SCFRDR2 Reading and the RDF Flag
Break Detection and Processing
Sending a Break Signal
Usage Notes
Rev. 4.00, 03/04, page 457 of 660