HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 145

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

5.1
5.1.1
The cache uses a 4-way set associative system. It is composed of four ways (banks), each of which
is divided into an address section and a data section. Each of the address and data sections is
divided into 256 entries. The data section of the entry is called a line. Each line consists of 16
bytes (4 bytes
16 kbytes in the cache as a whole (4 ways). Figure 5.1 shows the cache structure.
Instruction/data mixed, 16-byte cache
256 entries/way, 4-way set associative, 16-byte block
Write-back/write-through selectable
LRU replacing algorithm
1-stage write-back buffer
A maximum of two ways lockable
Entry 255
Entry 0
Entry 1
Cache Structure
Feature
.
.
.
.
.
.
24 (1 + 1 + 22) bits
V U Tag address
4). The data capacity per way is 4 kbytes (16 bytes
Address array (ways 0 to 3)
Figure 5.1 Cache Structure
Section 5 Cache
255
0
1
.
.
.
.
.
.
LW0
LW0 to LW3: Longword data 0 to 3
128 (32
LW1
4) bits
LW2
Data array (ways 0 to 3)
Rev. 4.00, 03/04, page 99 of 660
LW3
256 entries), with a total of
255
0
1
.
.
.
.
.
.
LRU
6 bits