HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 130

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

All general exception events occur in a relative order in the execution sequence of an instruction
(i.e. execution order), but are handled at priority level 2 in instruction-stream order (i.e. program
order), where an exception detected in a preceding instruction is accepted prior to an exception
detected in a subsequent instruction.
Three general exception events (reserved instruction code exception, unconditional trap, and
illegal slot instruction exception) are detected in the decode stage (ID stage) of different
instructions and are mutually exclusive events in the instruction pipeline. They have the same
execution priority. Figure 4.2 shows the order of general exception acceptance.
Rev. 4.00, 03/04, page 84 of 660
Figure 4.2 Example of Acceptance Order of General Exceptions
Pipeline Sequence:
Instruction n
Instruction n + 1
Instruction n + 2
Detection Order:
TLB miss (instruction n+1)
TLB miss (instruction n) and RIE (instruction n + 2) = simultaneous detection
Handling Order:
TLB miss (instruction n)
Re-execution of instruction n
TLB miss (instruction n + 1)
Re-execution of instruction n + 1
RIE (instruction n + 2)
Legend
IF
ID
EX
MA
WB
= Instruction fetch
= Instruction decode
= Instruction execution
= Memory access
= Write back
IF
ID
IF
TLB miss (instruction access)
EX
ID
IF
MA
EX
Program Order:
TLB miss (data access)
ID
RIE (reserved instruction exception)
WB
MA
EX
1
2
3
WB
MA
WB