HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 237

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HD6417706

Manufacturer Part Number
HD6417706
Description
Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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8.4.9
RTCNT is a 16-bit read/write register. RTCNT is an 8-bit counter that counts up with input clocks.
The clock select bits (CKS2 to CKS0) of RTCSR select the input clock. When RTCNT matches
RTCOR, the CMF bit of RTCSR is set and RTCNT is cleared. RTCNT is initialized to H'00 by a
power-on reset; it continues incrementing after a manual reset; it is not initialized by standby
mode and holds its values unchanged.
Note: Writing to the RTCNT differs from that to general registers to ensure the RTCNT is not
8.4.10
The refresh time constant register (RTCOR) is a 16-bit read/write register. The values of RTCOR
and RTCNT (bottom 8 bits) are constantly compared. When the values match, the CMF of
RTCSR is set and RTCNT is cleared to 0. When the refresh bit (RFSH) of the individual memory
control register (MCR) is set to 1 and the refresh mode is set to auto refresh, a memory refresh
cycle occurs when the CMF bit is set. RTCOR is initialized to H'00 by a power-on reset. It is not
initialized by a manual reset or standby mode, but holds its contents. Make the RTCOR setting
before setting bits CKS2 to CKS0 in RTCSR.
Note: Writing to the RTCOR differs from that to general registers to ensure the RTCOR is not
Bit
15 to 8
7 to 0
Bit
15 to 8
7 to 0
rewritten incorrectly. Use the word-transfer instruction to set the upper byte as
B'10100101 and the lower byte as the write data. For the byte-transfer instruction, writing
is disabled. Read data in 16 bits. 0 is read from undefined bits.
rewritten incorrectly. Use the word-transfer instruction to set the upper byte as
B'10100101 and the lower byte as the write data. For the byte-transfer instruction, writing
is disabled. Read data in 16 bits. 0 is read from undefined bits.
Refresh Timer Counter (RTCNT)
Refresh Time Constant Register (RTCOR)
Bit Name
Bit Name
Initial Value
Initial Value
All 0
All 0
All 0
All 0
R/W
R/W
R
R/W
R
R/W
Description
Reserved
These bits are always read as 0.
8-bit counter
Description
Reserved
These bits are always read as 0.
Upper limit of the counter (8 bits)
Rev. 4.00, 03/04, page 191 of 660

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