HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 262

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

A Tnop cycle, in which no operation is performed, is inserted before the Tc1 cycle in which the
READ command is issued in figure 8.19, but when synchronous DRAM is read, there is a two-
cycle latency for the DQMxx signal that performs the byte specification. If the Tc1 cycle were
performed immediately, without inserting a Tnop cycle, it would not be possible to perform the
DQMxx signal specification for Td1 cycle data output. This is the reason for inserting the Tnop
cycle. If the CAS latency is two cycles or longer, Tnop cycle insertion is not performed, since the
timing requirements will be met even if the DQMxx signal is set after the Tc1 cycle.
When bank active mode is set, if only accesses to the respective banks in the area 3 space are
considered, as long as accesses to the same row address continue, the operation starts with the
cycle in figure 8.18 or 8.21, followed by repetition of the cycle in figure 8.19 or 8.22. An access to
a different area 3 space during this time has no effect. If there is an access to a different row
address in the bank active state, after this is detected the bus cycle in figure 8.19 or 8.22 is
executed instead of that in figure 8.19 or 8.22. In bank active mode, too, all banks become inactive
after a refresh cycle or after the bus is released as the result of bus arbitration.
Rev. 4.00, 03/04, page 216 of 660
Address
upper bits
A12 or A11
Address
lower bits
CKIO
RD/
D31 to D0
Notes: 1.
or
2.
*
2
*
Command bit
Column address
1
Figure 8.18 Burst Read Timing (No Precharge)
Tr
Tc1
Tc2/Td1
Tc3/Td2
Tc4/Td3
Td4