HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 179

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Icyc:
Bcyc: Duration of one
Pcyc: Duration of one cycle of
Notes: 1. S also includes the memory access wait time.
Item
Response
time
Duration of one cycle of
2. Edge detection.
3. Extended modules: TMU, RTC, SCI, WDT, REFC
4. Extended modules: DMAC, ADC, SCIF
Total
Minimum
case
Maximum
case
The processing requiring the maximum execution time is LDC.L @Rm+, SR. When the
memory access is a cache-hit, this requires seven instruction execution cycles. When
the external access is performed, the corresponding number of cycles must be added.
There are also instructions that perform two external memory accesses; if the external
memory access is slow, the number of instruction execution cycles will increase
accordingly.
NMI
(5.5 + X)
+ 1.5
7
10.5 + S
Icyc
cycle of B
Bcyc
I
P
.
.
.
IRQ
(6.5 + X)
+ 0.5
+ 2
9
15.5 + S
Icyc
Pcyc*
Bcyc
Number of States
4
IRL
(5.5 + X)
+ 0.5
+ 3.5
9.5
20.5 + S
Icyc
Bcyc
Pcyc
Rev. 4.00, 03/04, page 133 of 660
Peripheral
Modules
(5.5 + X)
+ 1.5
(5.5 + X)
+ 3
7*
10.5 + S*
16.5 + S*
Icyc
Icyc
3
/8.5*
Pcyc*
Pcyc*
4
3
4
4
3
Notes
I : B : P = 1:1:1
I : B : P = 4:1:1