HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 333

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

9.6
9.6.1
In this example, DMA transfer is performed between the on-chip A/D converter (transfer source)
and the external memory (transfer destination) with address reload function on. Table 9.6 shows
the transfer conditions and register settings.
Table 9.6
When the address reload function is on, the values set in SAR_0 to SAR_3 returns to the initially
set value at each four transfers. In this example, when an interrupt request is generated from A/D
converter, longword data is read from the register in address H'04000080 in A/D converter, and it
is written to external memory address H'00400000. Since longword data has been transferred, the
values in SAR_2 and DAR_2 are H'04000084 and H'003FFFFC, respectively. The bus right is
maintained and data transfers are successively performed because this transfer is in the burst mode.
After four transfers end, fifth and sixth transfers are performed if the address reload function is off,
and the value in SAR_2 is incremented from H'0400008C, H'04000090, H'04000094,.... If the
address reload function is on, the DMA transfer stops after the fourth transfer ends, the bus request
signal to the CPU is cleared. At this time, the value stored in SAR_2 is not incremented from
H'0400008C to H'04000090, but returns to the initially set value H'04000080. The value in
DAR_2 continues being decremented regardless of whether the address reload function is on or
off.
As a result, the values in the DMAC are as shown in table 9.7 when the fourth transfer ends,
depending on whether the address reload function is on or off.
Transfer Conditions
Transfer source: on-chip A/D converter
Transfer destination: external memory
Number of transfers: 128 (reloading 32 times)
Transfer source address: incremented
Transfer destination address: decremented
Transfer request source: A/D converter
Bus mode: burst
Transfer unit: long word
Interrupt request generated at end of transfer
Channel priority order: 0 > 2 > 3 > 1
Example of DMA Transfer between A/D Converter and External Memory
Examples of Use
(Address Reload on)
Transfer Conditions and Register Settings for Transfer between On-Chip A/D
converter and External Memory
Register
SAR_2
DAR_2
DMATCR_2
CHCR_2
DMAOR
Rev. 4.00, 03/04, page 287 of 660
Setting
H'04000080
H'00400000
H'00000080
H'00089E35
H'0101