HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 156

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

5.4.3
1. Invalidating Specific Entries
2. Reading the Data of a Specific Entry
Rev. 4.00, 03/04, page 110 of 660
; R0 H'0110 0010; VPN B'00 0000 0100 0100 0000 0000, U 0, V 0
; R1 H'F000 0088; address array access, entry B'0000 1000, A 1
;
MOV.L R0,@R1
; R1 H'F100 004C; data array access, entry B'0000 0100, Way 0,
; longword address 3
;
MOV.L @R0,R1 ; Longword 3 is read.
Specific cache entries can be invalidated by writing 0 to the entry's U and V bit. When the A
bit is 1, the address tag specified by the write data is compared to the address tag within the
cache selected by the entry address, and data is written when a match is found. If no match is
found, there is no operation. When the V bit of the entry is 1, a write back occurs.
This example reads the data section of a specific cache entry. The longword indicated in the
data field of the data array in figure 5.6 is read to the register.
Usage Examples