HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 195

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

7.3.2
1. When CPU/instruction fetch/read/word or longword is set in the break bus cycle registers
2. An instruction set for a break before execution breaks when it is confirmed that the instruction
3. When the condition is specified to be occurred after execution, the instruction set with the
4. When an instruction fetch cycle is set for channel B, break data register B (BDRB) is ignored.
7.3.3
1. The memory cycles in which CPU data access breaks occur are from instructions.
2. The relationship between the data access cycle address and the comparison condition for
Table 7.1
3. When the data value is included in the break conditions on B channel:
Access Size
Longword
Word
Byte
(BBRA/BBRB), the break condition becomes the CPU instruction fetch cycle. Whether it then
breaks before or after the execution of the instruction can then be selected with the
PCBA/PCBB bits of the break control register (BRCR) for the appropriate channel.
has been fetched and will be executed. This means this feature cannot be used on instructions
fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to
be executed). When this kind of break is set for the delay slot of a delay branch instruction, the
break is generated prior to execution of the instruction that then first accepts the break.
Meanwhile, the break set for pre-instruction-break on delay slot instruction and post-
instruction-break on SLEEP instruction are also prohibited.
break condition is executed and then the break is generated prior to the execution of the next
instruction. As with pre-execution breaks, this cannot be used with overrun fetch instructions.
When this kind of break is set for a delay branch instruction, the break is generated at the
instruction that then first accepts the break.
There is thus no need to set break data for the break of the instruction fetch cycle.
operand size are listed in table 7.1:
This means that when address H'00001003 is set without specifying the size condition, for
example, the bus cycle in which the break condition is satisfied is as follows (where other
conditions are met).
Longword access at H'00001000
Word access at H'00001002
Byte access at H'00001003
Break on Instruction Fetch Cycle
Break by Data Access Cycle
Data Access Cycle Addresses and Operand Size Comparison Conditions
Address Compared
Compares break address register bits 31 to 2 to address bus bits 31 to 2
Compares break address register bits 31 to 1 to address bus bits 31 to 1
Compares break address register bits 31 to 0 to address bus bits 31 to 0
Rev. 4.00, 03/04, page 149 of 660