HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 66

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

2.2
2.2.1
Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits)
or a word (16 bits), the sign is extended to the longword, and stores into the register.
2.2.2
Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in
8-bit byte, 16-bit word, or 32-bit longword form. A memory operand less than 32 bits in length is
sign-extended before being stored in a register.
A word operand must be accessed starting from a word boundary (even address of a 2-byte unit:
address 2n), and a longword operand starting from a longword boundary (even address of a 4-byte
unit: address 4n). An address error will result if this rule is not observed. A byte operand can be
accessed from any address.
Big-endian or little-endian byte order can be selected for the data format. The endian mode should
be set with the MD5 external pin in a power-on reset. Big-endian mode is selected when the MD5
pin is low, and little-endian when high. The endian mode cannot be changed dynamically. Bit
positions are numbered left to right from most-significant to least-significant. Thus, in a 32-bit
longword, the leftmost bit, bit 31, is the most significant bit and the rightmost bit, bit 0, is the least
significant bit.
Rev. 4.00, 03/04, page 20 of 660
Global Base Register (GBR)
Stores base address of GBR-indirect addressing mode. The GBR-indirect addressing mode is
used for on-chip supporting module register area data transfers and logic operations.
The GBR register can also be accessed in user mode.
Vector Base Register (VBR)
Stores base address of exception handling vector area.
Initialized to H'0000000 by a reset.
Initialized to undefined by a reset.
Data Formats
Data Format in Registers
Data Format in Memory
31
Longword
0