MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 1081

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

16.9.5
This is an Embedded USB Host Controller as defined by the EHCI specification and thus does not
implement the PCI configuration registers.
16.9.5.1
Given that the optional PCI configuration registers are not included in this implementation, there is no
corresponding bit level timing adjustments like those provided by the Frame Adjust register in the PCI
configuration registers. Starts of microframes are timed precisely to 125 µsec using the transceiver clock
as a reference clock. That is, 60 MHz transceiver clock for 8-bit physical interfaces and full-speed serial
interfaces or 30 MHz transceiver clock for 16-bit physical interfaces.
16.9.6
16.9.6.1
The modules support multiple physical interfaces which can operate in different modes when the module
is configured with the software programmable Physical Interface Modes. The control bits for selecting the
PHY operating mode have been added to the PORTSC register providing a capability that is not defined
by the EHCI specification.
16.9.6.2
16.9.6.2.1
The port connect methods specified by EHCI require setting the port reset bit in the register for a duration
of 10 msec. Due to the complexity required to support the attachment of devices that are not high speed
there are counter already present in the design that can count the 10 msec reset pulse to alleviate the
requirement of the software to measure this duration. Therefore, the basic connection is then summarized
as the following:
Freescale Semiconductor
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[Port Change Interrupt] Port connect change occurs to notify the host controller driver that a device
has attached.
Software shall write a ‘1’ to the reset the device.
Software shall write a ‘0’ to the reset the device after 10 msec.
— This step, which is necessary in a standard EHCI design, may be omitted with this
[Port Change Interrupt] Port enable change occurs to notify the host controller that the device in
now operational and at this point the port speed has been determined.
implementation. Should the EHCI host controller driver attempt to write a ‘0’ to the reset bit
while a reset is in progress the write will simple be ignored and the reset will continue until
completion.
Embedded Design
Miscellaneous Variations from EHCI
Frame Adjust Register
Programmable Physical Interface Behavior
Discovery
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Port Reset
Universal Serial Bus Interface
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