MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 521

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

The RAM array contains 64 words of 32-bits each. The signal timing generator loads the RAM word from
the RAM array to drive the general-purpose lines, byte-selects, and chip-selects. If the UPM reads a RAM
word with WAEN set, the external LUPWAIT signal is sampled and synchronized by the memory
controller and the current request is frozen.
10.4.4.1
A special pattern location in the RAM array is associated with each of the possible UPM requests. An
internal device’s request for a memory access initiates one of the following patterns (M
A UPM refresh timer request pattern initiates a refresh timer pattern (RTS).
An exception (caused by a bus monitor time-out error) occurring while another UPM pattern is running
initiates an exception condition pattern (EXS).
Figure 10-59
cycle type. RUN commands (M
UPM RAM words.
Freescale Semiconductor
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•
•
•
Read single-beat pattern (RSS)
Read burst cycle pattern (RBS)
Write single-beat pattern (WSS)
Write burst cycle pattern (WBS)
Exception Condition Request
UPM Requests
and
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Read Single-Beat Request
Write Single-Beat Request
Table 10-39
Refresh Timer Request
Read Burst Request
Write Burst Request
Read single-beat (RSS)
Read burst (RBS)
Write single-beat (WSS)
Write burst (WBS)
show the start addresses of these patterns in the UPM RAM, according to
Table 10-39. UPM Routines Start Addresses
x
MR[OP] = 11), however, can initiate patterns starting at any of the 64
UPM Routine
Figure 10-59. RAM Array Indexing
Array Index
Generator
WSS
WBS
RSS
RBS
EXS
RTS
Routine Start Address
0x00
0x08
0x18
0x20
RAM Array
Enhanced Local Bus Controller
64 RAM
Words
x
MR[OP] = 00):
10-73