MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 644
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Security Engine (SEC) 2.2
14.1
The SEC 2.2 (referred to as SEC in this chapter) can act as a master on the internal system bus to allow the
SEC to off-load the data movement bottleneck normally associated with slave-only cores. The host
processor accesses the SEC through its device drivers using system memory for data storage. The SEC
resides in the peripheral memory map of the processor, therefore when an application requires
cryptographic functions, it simply creates descriptors for the SEC which define the cryptographic function
to be performed and the location of the data. The SEC’s bus-mastering capability permits the host
processor to set up the channel with a few short register writes, leaving the SEC to perform reads and
writes on system memory to complete the required task.
14-2
•
•
System Bus
— 256-byte buffer FIFOs on data input and output paths of each execution unit, with flow control
Master/slave logic, with DMA
— 32-bit address/64-bit data
— DMA blocks can be on any byte boundary
Scatter/Gather capability
— Gather capability enables the SEC 2.2 to concatenate multiple segments of memory when
— Similarly, scatter capability enables the SEC 2.2 to write to multiple segments of memory when
SEC 2.2 Architecture Overview
for large data sizes. The input and output FIFOs are shared between AESU and DEU; MDEU
has its own input FIFO.
reading input data
writing output data
16K-I
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
e300
Core
16K-D
Figure 14-1. SEC Connected to MPC8313E System Bus
DUART
Timers
I
2
C
DDR-1/DDR-2
Controller
eLBC
IPIC
I/O Sequencer (IOS)
PCI
Security
DMA
Freescale Semiconductor
GPIO
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