MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 900

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
The first TxBD[TOE] bit is set. When the TMR_CTRL[Record Timestamp In PAL Enable] and
TxFCB[PTP] bits are set, the timestamp is written to memory location TxBD[Data Buffer Pointer]+16.
The second TxBD’s Data Length must either contain the full frame length, or a value greater than the
TxThreshold setting. Refer to
TMR_TXTSn_H/L and TMR_TXTSn_ID registers still function normally.
15.6.6.5.1
The TxPAL is updated with a timestamp before closing the second TxBD. The TxBD[I] bit can be set for
the second TxBD frame to cause an interrupt (via IEVENT[TXF]) after the timestamp has been written to
the TxPAL.
When timestamps are inserted into the TxPAL, the TMR_TXTSn_H/L and TMR_TXTSn_ID registers
still function normally. Therefore, the 1588 interrupt can be triggered by using the TMR_PEVENT register
bits TXP1, and TXP2.
15-182
TMR_CTRL[RTPE]=1
TxBD[TOE]=1
First TxBD[Data Buffer Pointer] is 8-byte aligned
First TxBD[Data Length]=8, 8 bytes for TxFCB
TxFCB[PTP]=1
The TxFCB is followed immediately by a minimum of 16 bytes
for the TxPAL
Second TxBD[Data Buffer Pointers] points to start of L2 or
frame data
Second TxBD[Data Length] >= FIFO_TX_THR or includes the
entire frame
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Interrupts
Requirement
Table 15-161. Timestamp Insertion Programming Requirements
Table
15-161. When timestamps are inserted into the TxPAL, the
If TMR_CTRL[RTPE]=0, then no timestamp is written to a
TxPAL.
If TxBD[TOE]=0, then no timestamp is written to a TxPAL.
The timestamp will be written to address First TxBD[Data
Buffer Pointer] + 0x10 rounded down to the nearest 8-byte
aligned address, except at 4K page boundaries, in which case
the timestamp may be invalid, and the Second TxBD close
status will be lost.
If L2 or frame data is included in the Length, the buffer
immediately following the FCB is transmitted on the line and
the frame data stored in memory will be overwritten with a
timestamp value after the frame is transmitted.
If TxBD[PTP]=0, then no timestamp is written to a TxPAL.
The timestamp will be written to address First TxBD[Data
Buffer Pointer] + 0x10.
If there is only one TxBD used to transfer a PTP frame, then no
timestamp is written to a TxPAL.
If this condition is not true, the timestamp in TxPAL is invalid.
Behavior if requirement is not met
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