MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 504
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Enhanced Local Bus Controller
10.4.2.5
Boot chip-select operation allows address decoding for a boot ROM before system initialization. LCS0 is
the boot chip-select output; its operation differs from other external chip-select outputs after a system reset.
When the core begins accessing memory after system reset, LCS0 is asserted for every local bus access
until BR0 or OR0 is reconfigured.
The boot chip-select also provides a programmable port size, which is configured during reset. The boot
chip-select does not provide write protection. LCS0 operates this way until the first write to OR0 and it
can be used as any other chip-select register after the preferred address range is loaded into BR0. After the
first write to OR0, the boot chip-select can be restarted only with a hardware reset.
the initial values of the boot bank in the memory controller.
10-56
LBCTL
LCS n
LCLK
LALE
LGTA
LAD
LOE
TA
GPCM Boot Chip-Select Operation
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
A
Table 10-34. Boot Bank Field Values after Reset for GPCM as Boot Controller
Address
Figure 10-43. External Termination of GPCM Access
Register
BR0
Latched Address
DECC
MSEL
ATOM
Field
WP
PS
BA
V
0000_0000_0000_0000_0
From RCWH[ROMLOC]
Read Data
Setting
000
00
00
0
1
Table 10-34
Freescale Semiconductor
describes
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