MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 373

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 8-12
8.5.6
Each implemented bit in SIMSR_H and SIMSR_L, shown in
internal interrupt source. The user masks an interrupt by clearing the corresponding SIMSR bit. When an
interrupt request occurs, the corresponding SIPNR bit is set, regardless of the SIMSR bit. However, if the
corresponding SIMSR bit is cleared, no interrupt request is passed to the core.
When an SIMSR bit is cleared by the user at the same time corresponding interrupt source requests an
interrupt service, the request stops. If the user sets the SIMSR bit later, the core processes any pending
corresponding interrupt requests according to its priority.
Freescale Semiconductor
12–15,
Offset 0x20
Reset
16–27
28–31
3–11,
Bits
0–2
W
R
0
SYSD1P–
SYSD0P SYSD0 priority order. Defines which interrupt source asserts its request in the SYSD0 priority position. The
SYSD7P
Name
—
defines the bit fields of SIPRR_D.
System Internal Interrupt Mask Register (SIMSR_H and SIMSR_L)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
user should not program the same code to more than one priority position (0–7). These bits can be changed
dynamically. SYSD0P is defined as follows:
000 UART1 asserts its request in the SYSD0 position.
001 UART2 asserts its request in the SYSD0 position.
010 SEC asserts its request in the SYSD0 position.
011 eTSEC1 1588 timer asserts its request in the SYSD0 position.
100 eTSEC2 1588 timer asserts its request in the SYSD0 position.
101 I2C1 asserts its request in the SYSD0 position.
110 I2C2 asserts its request in the SYSD0 position.
111 SPI asserts its request in the SYSD0 position.
Same as SYSD0P, but for SYSD1P–SYSD7P.
Write ignored, read = 0
Figure 8-8. System Internal Interrupt Mask Register (SIMSR_H)
Table 8-12. SIPRR_D Field Descriptions
INT
n (Implemented bits are listed in
All zeros
Description
Figure 8-8
Integrated Programmable Interrupt Controller (IPIC)
Table
8-7.)
and
Figure
8-9, corresponds to an
Access: Read/write
8-15
31