MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 971
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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16.3.2.27 System Interface Control Register (SI_CTRL)—Non-EHCI
Note that this register uses big-endian byte ordering and is not defined in the EHCI specification. The
system interface control register (SI_CTRL) controls various functions pertaining to the internal system
interface.
16.3.2.28 USB General Purpose Register (CONTROL)—Non-EHCI
Note that this register uses big-endian byte ordering and is not defined in the EHCI specification. The USB
general purpose (CONTROL) register contains the general-purpose IP control register outputs and is
shown in
Freescale Semiconductor
Offset 0x2_3410
Reset
28–29
30–31
28–30
0–27
0–26
Bits
Bits
27
31
W
R
0
rd_prefetch_val Selects whether 32 bytes or 64 bytes are fetched during burst read transactions at the system
Figure
pri_lvl1
pri_lvl0
err_disable
Name
—
Name
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
—
—
16-34.
Reserved, should be cleared
Priority level for priority state 1.
Priority level for priority state 0.
Reserved, should be cleared
When this bit is set, it causes the controller to ignore system bus errors. If cleared the controller
responds according to the values set in USBSTS[SEI] and USBINT[SEE].
0 enable
1 disable
Reserved, should be cleared
interface. When this input is LOW 64 bytes are fetched and when it is HIGH 32 bytes are fetched.
The setting of rd_prefetch_val must match the setting of the larger of TXPBURST and RXPBURST
fields in the BURSTSIZE register. If either of these fields is 64 bytes, then rd_prefetch_val must be
left cleared. Otherwise, this value should be set.
0 64-byte fetch
1 32-byte fetch
Figure 16-33. System Interface Control Register (SI_CTRL)
Table 16-35. PRI_CTRL Register Field Descriptions
Table 16-36. SI_CTRL Register Field Descriptions
—
All zeros
Description
Description
26
disable
err_
27
28
Universal Serial Bus Interface
—
Access: Read/Write
30
rd_prefetch
_val
31
16-43
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