MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 710
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Security Engine (SEC) 2.2
14.6.4.2
The SEC controller generates the single interrupt output from all possible interrupt sources. These sources
can be individually enabled by the interrupt mask register (IMR). If unmasked, the interrupt source value,
when active, is captured into the interrupt status register (ISR).
each potential interrupt source. Each interrupt source is individually unmasked by setting its corresponding
bit. At reset, all bits are disabled. The bit fields are described in
For normal operation, the IMR should be programmed as follows: Unmask the channel interrupts while
masking EU interrupts. The channels will generate the appropriate interrupts to the host.
14-68
Rese
Rese
Field
Addr
Field
Addr
R/W
R/W
t
t
32
0
0xF
—
Interrupt Mask Register (IMR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
35
3
36
4
0x0
—
Figure 14-41. EU Assignment Status Register (EUASR)
39
7
0xFFF0
—
40
8
0xF
—
11
43
12–14
0x0
—
44
MDEU
0x3_ 102C
0x 3_1028
15
47
0
R
R
16
48
0xF
0xF
—
—
Figure 14-42
19
51
Table
20–22
0x0
—
52
14-39.
0x0
—
AESU
23
55
0
shows the bit positions of
24
56
Freescale Semiconductor
0xF
0xF
—
—
27
59
28–30
0x0
—
60
0x0
—
DEU
31
63
0
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