MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 710

Manufacturer Part Number

MPC8313ECZQADDC

Microprocessors - MPU 8313 REV2.2 PB ENC EXT

Manufacturer

Freescale Semiconductor

Processor Series

Data Bus Width

Maximum Clock Frequency

Program Memory Size

Data Ram Size

Interface Type

Mounting Style

Package / Case

Number Of Programmable I/os

Number Of Timers

Security Engine (SEC) 2.2

The SEC controller generates the single interrupt output from all possible interrupt sources. These sources

can be individually enabled by the interrupt mask register (IMR). If unmasked, the interrupt source value,

when active, is captured into the interrupt status register (ISR).

each potential interrupt source. Each interrupt source is individually unmasked by setting its corresponding

bit. At reset, all bits are disabled. The bit fields are described in

For normal operation, the IMR should be programmed as follows: Unmask the channel interrupts while

masking EU interrupts. The channels will generate the appropriate interrupts to the host.

Interrupt Mask Register (IMR)

MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2

Figure 14-41. EU Assignment Status Register (EUASR)

Figure 14-42

shows the bit positions of

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