MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 170

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Reset, Clocking, and Initialization
4.2
This section describes the various ways to reset the device, the power-on reset configurations, and
clocking.
4.2.1
The device has several inputs to the reset logic:
4-4
USB_CR_CLK_OUT
PCI_CLK_OUT[0:2]
PCI_SYNC_OUT
PCI_SYNC_IN
•
•
•
•
•
•
PCI_CLK/
Signal
Power-on reset (PORESET)
External hard reset (HRESET)
External soft reset (SRESET)
Software watchdog reset
System bus monitor reset
Checkstop reset
Functional Description
Reset Operations
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
I/O
O
O
O
I
USB crystal output. USB_CR_CLK_IN/USB_CR_CLK_OUT allows the USB clock to be provided
through an external crystal oscillator. If a crystal source is used, USB_CLK_IN should be tied low.
Requirements Should be left unconnected if unused, for example when the clock is provided
PCI clock/ PCI synchronization clock (PCI_CLK/PCI_SYNC_IN). PCI_CLK is the primary clock
input to the device, the reference clock for the system APLL. When the device is in PCI host mode
SYS_CLK_IN or SYS_CR_CLK_IN is used as the clock source. In this case the
PCI_CLK_OUT[0:2] signals are driven and PCI_SYNC_IN should be tied to PCI_SYNC_OUT.
When the device is in PCI agent mode PCI_CLK will be tied directly to a PCI system clock source.
Reference PCI output synchronization clock (PCI_SYNC_OUT). In PCI host mode with the
PCI_CLK_OUT[0:2] signals driven, PCI_SYNC_OUT is connected externally to PCI_SYNC_IN
signal for de-skewing external PCI clocks routing. PCI_SYNC_OUT has the same frequency as
CLKIN or CLKIN/2 depending on the state of CFG_CLKIN_DIV at reset. See
“SYS_CLK_IN Division.”
PCI output clocks bank. In PCI host mode, the device provides three separate clock output signals
for feeding PCI agent devices.
Reset State Always output.
Reset State Always input.
Reset State Always output, toggling in PCI host mode.
Reset State Always output. Drive ‘0’ and after power-on reset flow. Enabled by a
Table 4-2. External Clock Signals (continued)
Timing Assertion/Negation—See the hardware specifications for timing information
Timing Assertion/Negation—See the hardware specifications for timing information
Timing Assertion/Negation—See the hardware specifications for timing information.
Timing Assertion/Negation—See the hardware specifications for timing information.
through USB_CR_CLK_IN or when derived from the system clock.
memory-mapped register.
In PCI agent mode, this signal is typically not used.
Description
Freescale Semiconductor
Section 4.3.1.2,