MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 1210
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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S–S
Reset and clocking blocks
RMON support, see eTSEC, modes of operation
Index-12
DDR debug configuration, 5-26
functional device description, 5-33, 5-61, 5-72
hard reset (HRESET)
memory map/register definition, 4-32
operations, 4-4
PCI output hold configuration, 4-21
power-on reset (POR)
registers
signals, 4-1–4-2
soft reset (SRESET)
soft reset actions
boot ROM location, 4-18
boot sequencer configuration, 4-17
CPU boot configuration, 4-15
external signal description, 5-43, 5-51, 5-65
functional description, 4-4, 5-33, 5-61, 5-72
host/agent configuration, 4-16
memory map/register definition, 5-30, 5-37, 5-44, 5-52
system PLL ratio, 4-30
TSEC width, 4-19
boot memory space, 4-17
boot ROM location, 4-18
boot sequencer, 4-17
CLKIN division, 4-11
default words, 4-26
e300 core true little endian mode, 4-20
LALE, 4-21
loading from I
loading words, 4-21
PCI host/agent, 4-16
selecting input signals, 4-11
signals, 4-9
TSEC1 mode, 4-19
TSEC2 mode, 4-20
words, 4-12
words source, 4-10
flow, 4-8
flow, 4-6
timing diagram, 4-8
configuration, 4-13, 4-32–4-37
flow, 4-9
and reconfiguring the eTSEC, 15-145
hard coded reset configuration words usage examples,
boot sequencer, 4-23
calling address, 4-23
data format in reset configuration mode, 4-23
load fail, 4-25
from local bus EEPROM, 4-21
4-27
2
C EEPROM, 4-23
MPC8313E PowerQUICC™ II Pro Integrated Processor Reference Manual, Rev. 2
S
SCL (I
SDA (I
SEC
Security engine
Segment registers (SRn), 7-19
Serial data/clock wires, 17-1
Serial peripheral interface, see SPI
Signals
bus interface
power saving mode, 14-75
block diagram, 1-10
overview, 1-10
clock, 4-3–4-4
complete signal listing
configuration, sampled at reset, 3-12
control, description, 5-36, 5-44, 5-52, 5-65
DDR
DUART, 18-3–18-4
eset and clocking blocks, 5-43, 5-65
eTSEC
interrupts, 14-75
PCI_CLK, 4-4
PCI_CLK_OUT[0:7], 4-4, 4-30
PCI_SYNC_IN, 4-4
PCI_SYNC_OUT[0:7], 4-4
SYS_CLK_IN, 4-3
USB_CLK_IN, 4-3
reference by functional block, 3-3–3-12
MA[0:14] (address bus), 9-6
MBA[0:1] (logical bank address), 9-6
MCAS (column address strobe), 9-6
MCK[0:5] (DDR clock output complements), 9-7
MCK[0:5] (DDR clock outputs), 9-7
MCKE[0:3] (DDR clock enables), 9-8
MCS[0:3] (chip selects), 9-7
MDM[0:8] (SDRAM data output mask), 9-7
MDQS[0:8] (data bus strobes), 9-5, 9-30
MODT[0:3] (on-die termination), 9-7
MRAS (row address strobe), 9-6
MWE (write enable), 9-7
UART_CTS[0:1] (DUART clear to send), 18-1, 18-3,
UART_RTS[0:1] (DUART request to send), 18-1, 18-3,
UART_SIN [0:1] (DUART transmitter serial data in),
UART_SOUT [0:1] (DUART transmitter serial data
EC_GTX_CLK125 (eTSEC gigabit transmit 125 MHz
2
2
C serial clock) signal, 17-3, 17-4
C serial data) signal, 17-3, 17-4
18-4
18-4
18-3
out), 18-3, 18-4
source), 15-9
Freescale Semiconductor
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