MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 934

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
16-6
0x2_3000–
0x2_31AC
0x2_31BC
0x2_30FF
0x2_314C
0x2_31A4
0x2_31A8
0x2_31B0
0x2_31B4
0x2_31B8
0x2_31C0
0x2_31C4
0x2_31C8
0x2_3100
0x2_3102
0x2_3104
0x2_3108
0x2_3120
0x2_3124
0x2_3140
0x2_3144
0x2_3148
0x2_3154
0x2_3158
0x2_3160
0x2_3164
0x2_3170
0x2_3180
0x2_3184
Offset
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved, should be cleared
CAPLENGTH—Capability register length
HCIVERSION—Host interface version number
HCSPARAMS—Host crtl. structural parameters
HCCPARAMS—Host crtl. capability parameters
DCIVERSION—Device interface version number
DCCPARAMS—Device controller parameters
USBCMD—USB command
USBSTS—USB status
USBINTR—USB interrupt enable
FRINDEX—USB frame index
PERIODICLISTBASE—Frame list base address
DEVICEADDR—USB device address
ASYNCLISTADDR—Next asynchronous list addr (host
mode)
ENDPOINTLISTADDR—Address at endpoint list (device
mode)
BURSTSIZE—Programmable burst size
TXFILLTUNING—Host TT transmit pre-buffer packet
tuning
ULPI VIEWPORT—ULPI Register Access
CONFIGFLAG—Configured flag register
PORTSC—Port status/control
OTGSC—On-The-Go status and control
USBMODE—USB device mode
ENDPTSETUPSTAT—Endpoint setup status
ENDPOINTPRIME—Endpoint initialization
ENDPTFLUSH—Endpoint de-initialize
ENDPTSTATUS—Endpoint status
ENDPTCOMPLETE—Endpoint complete
ENDPTCTRL0—Endpoint control 0
ENDPTCTRL1—Endpoint control 1
ENDPTCTRL2—Endpoint control 2
1
Table 16-3. USB Interface Memory Map
Register
USB DR Controller Registers
1
1
1
1
1
Access
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
—
R
R
R
R
R
R
R
R
0x0000‘_0001
0x0000_0C20
0x0001_0011
0x0000_0006
0x0000_0183
0x0008_0000
0x0000_0000
0x0000_0000
0x0000_ nnnn
0x nnnn _0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_1010
0x0000_0000
0x0000_0000
0x1000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0080_0080
0x0000_0000
0x0000_0000
0x0100
0x0001
Reset
0x40
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