MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 243

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Although most software disciplines permit or even encourage the watchdog concept, some systems require
a selection of time-out periods. For this reason, the software watchdog timer must provide a selectable
range for the time-out period.
Figure 5-23
into a 16-bit decrementer clocked by the system clock. An additional divide-by-65,536 prescaler value is
used when needed.
The decrementer begins counting when loaded with a value from SWTC. After the timer reaches 0x0, a
software watchdog expiration request is issued to the reset or mcp (machine check) control logic. Upon
reset, SWTC is set to the maximum value and is again loaded into the system watchdog service register
(SWSRR), starting the process over. When a new value is loaded into SWTC, the software watchdog timer
is not updated until the servicing sequence is written to the SWSRR. If SWCRR[SWEN] is loaded with 0,
the modulus counter does not count.
5.4.5.2
The WDT unit can operate in the following modes:
Freescale Semiconductor
•
•
Clocking
System
WDT enable/disable mode:
If the software watchdog timer is not needed, the user can disable it. The SWCRR[SWEN] bit
enables the watchdog timer. It should be cleared by software after a system reset to disable the
software watchdog timer. When the watchdog timer is disabled, the watchdog counter and
prescaler counter are held in a stopped state.
— WDT enable mode (SWCRR[SWEN] = 1)
— WDT disable mode (SWCRR[SWEN] = 0)
WDT reset/interrupt output mode
Without software periodic servicing, the software watchdog timer times out and issues a reset or a
nonmaskable interrupt (mcp), programmed in SWCRR[SWRI].
According to the value of SWCRR[SWRI], the WDT timer causes a hard reset or machine check
interrupt to the core.
This is the default value after soft reset.
shows that the range is determined by SWCRR[SWTC]. The value in SWTC is then loaded
Modes of Operation
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
SWCRR[SWEN]
Disable
Clock
Figure 5-23. Software Watchdog Timer Functional Block Diagram
Figure 5-23
65,536
Divider
shows how to handle this need.
SWCRR[SWPR]
16-Bit Decrementer
SWCRR[SWTC]
SWSRR[WS]
SWCNR
Service
Reload
Time-out
SWCRR[SWRI]
System Configuration
or mcp
Reset
Event
Logic
5-35