MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 1184
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Revision History
10.3.1.9, 10-26
10.3.1.12, 10-31
10.3.1.15, 10-34
10.4.2.5, 10-58
10.4.3.4.1, 10-71
10.4.3.4.3, 10-74
12.3.8.1, 12-11
13.3.3.13, 13-33
13.3.3.5, 13-30
14.1, 14-1
14.3.2, 14-12
14.3.2.2, 14-15
14.3.4, 14-17
14.3.4, 14-18
14.4, 14-20
14.4.2.11, 14-40
14.4.3.1, 14-41
14.4.3.6, 14-47
14.5.1.2, 14-62
14.5.1.2, 14-63
A-26
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Added the following statement at the end of the current description:
After any error/event reported by LTESR, LTEATR[V] must be cleared for
LTESR to update again.
Added LTESR in the list of registers to be cleared by software once LTEATR[V]
is set.
In Table 10-21, for bit LCRR[PBYP, removed ‘if the PLL is unable to lock.
Clarified for bit LCRR[EADC], LCLK.’ Added line to LCRR[CLKDIV], ‘The
system clock can be equal to csb_clk or twice csb_clk ( if RCWL[LBIUCM] is
set.’
In Table 10-31, Register BR0, corrected the source to be from
RCWH[ROMLOC], not POR cfg pin.
In Table 10-35, Register OR0, corrected the source to be from
RCWH[ROMLOC], not POR cfg pin. Also corrected the setting of OR0 SCY to
010 from 011.
Removed this section.
In Table 12-10, added the following note to fields DAHE and SAHE:
The DMA does not support address hold when the external trigger mode is
selected (EMSEN = 1).
Modified PIMMR from 28 to 12 writeable bits.
In Table 13-27 replaced the chip revision ID with 8’h10.
Removed SEC frequency information from the bulletted list of features in the
introduction.
Second paragraph, last line should read, ‘and described in Table 14-6.’
In Table 14-7, added a note to AESU CTR non-snooping.
Third paragraph, replaced ‘36-bit’ with ‘32-bit.’
In Table 14-10, changed bits 24–31 to ‘Reserved.’ In second paragraph, replaced
reference to Figure 14-7 with Figure 14-6.
Replaced ‘are used in SEC,’ with ‘are used in SEC 2.2.’
Figure 14-25, added SHA-224 to the Name column, between SHA-1 and
SHA-256.
Change the third paragraph to read:
Table 14-25 describes AESUMR fields.
Change the second paragraph to read:
Table 14-29 describes AESUISR fields.
Table 14-35 changed the title of the table to read: ‘Crypto-Channel Pointer Status
Register Error Field Definitions.’
Change the first paragraph after Table 14-36 with the following:
Table 14-36 shows the possible values of the PAIR_PTR field in the CCPSR.
Freescale Semiconductor
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