MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 43

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Figure
Number
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
10-13
10-14
10-15
10-16
10-17
10-18
10-19
10-20
10-21
10-22
10-23
10-24
10-25
10-26
10-27
10-28
10-29
10-30
10-31
10-32
10-33
10-34
10-35
10-36
10-37
10-38
Freescale Semiconductor
Base Registers (BRn) .......................................................................................................... 10-10
Basic eLBC Bus Cycle with LALE, TA, and LCSn ........................................................... 10-43
Option Registers (ORn) in GPCM Mode............................................................................ 10-13
Option Registers (ORn) in FCM Mode............................................................................... 10-15
Option Registers (ORn) in UPM Mode .............................................................................. 10-18
UPM Memory Address Register (MAR) ............................................................................ 10-19
UPM Mode Registers (MxMR)........................................................................................... 10-20
Memory Refresh Timer Prescaler Register (MRTPR)........................................................ 10-22
UPM Data Register in UPM Mode (MDR) ........................................................................ 10-23
FCM Data Register in FCM Mode (MDR)......................................................................... 10-23
Special Operation Initiation Register (LSOR) .................................................................... 10-24
UPM Refresh Timer (LURT) .............................................................................................. 10-24
Transfer Error Status Register (LTESR) ............................................................................. 10-25
Transfer Error Check Disable Register (LTEDR) ............................................................... 10-27
Transfer Error Interrupt Enable Register (LTEIR).............................................................. 10-28
Transfer Error Attributes Register (LTEATR...................................................................... 10-29
Transfer Error Address Register (LTEAR) ......................................................................... 10-30
Transfer Error ECC Register (LTECCR) ............................................................................ 10-31
Local Bus Configuration Register....................................................................................... 10-31
Clock Ratio Register (LCRR) ............................................................................................. 10-33
Flash Mode Register ........................................................................................................... 10-34
Flash Instruction Register ................................................................................................... 10-36
Flash Command Register .................................................................................................... 10-36
Flash Block Address Register ............................................................................................. 10-37
Flash Page Address Register, Small Page Device (ORx[PGS] = 0) ................................... 10-37
Flash Page Address Register, Large Page Device (ORx[PGS] = 1) ................................... 10-38
Flash Byte Count Register .................................................................................................. 10-39
Flash ECC Blockn Register (FECC0–FECC3)................................................................... 10-40
Basic Operation of Memory Controllers in the eLBC ........................................................ 10-41
Example of 8-Bit GPCM Writing 32 Bytes to Address 0x5420 (LCRR[PBYP] = 0) ........ 10-43
Enhanced Local Bus to GPCM Device Interface................................................................ 10-45
GPCM Basic Read Timing (XACS = 0, ACS = 1x, TRLX = 0, CLKDIV = 4,8) .............. 10-46
GPCM General Read Timing Parameters ........................................................................... 10-46
GPCM General Write Timing Parameters .......................................................................... 10-48
GPCM Basic Write Timing (XACS = 0, ACS = 00, CSNT = 1,
GPCM Relaxed Timing Back-to-Back Reads (XACS = 0, ACS = 1x,
GPCM Relaxed Timing Back-to-Back Writes (XACS = 0, ACS = 1x,
SCY = 1, TRLX = 0, CLKDIV = 4, 8) .......................................................................... 10-50
SCY = 1, CSNT = 0, TRLX = 1, EHTR = 0, CLKDIV = 4, 8) ..................................... 10-52
SCY = 0, CSNT = 0, TRLX = 1, CLKDIV = 4, 8) ........................................................ 10-52
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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