MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 1103

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

17.4.5.4
Dedicated hardware is not provided to indicate whether the boot sequencer operation completed
successfully. It is recommended to use one of the GPIO signals for that purpose. To do this, the last register
preload programmed into the EEPROM should contain the address of the appropriate GPIO register and
data that causes the setting of the required GPIO signal. The GPIO signal may be used for an external
device or for debug purposes.
17.5
This section describes some programming guidelines recommended for the I
a recommended flowchart for I
A sync assembly instruction must be executed after each I
register accesses occur in order.
The I
malfunctioning device may hold the bus captive. A good programming practice is for software to rely on
a watchdog timer to help recover from I
when the illegal I
what was expected.
17.5.1
Figure 17-11
flowchart may result in unpredictable I
the interrupt service routine may need to set I2CnCR[TXAK] when the next-to-last byte is to be accepted.
It is recommended that a sync instruction follow each I
accesses occur in order.
Freescale Semiconductor
2
C controller does not guarantee its recovery from all illegal I
Initialization/Application Information
Interrupt Service Routine Flowchart
Boot Sequencer Done Indication
shows an example algorithm for an I
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
2
C bus behavior causes the status bits returned after an interrupt to be inconsistent with
2
C interrupt service routines.
2
C bus behavior. However, in the slave receive mode (not shown),
2
C bus hangs. The recovery routine should also handle the case
2
C interrupt service routine. Deviation from the
2
C register read or write to guarantee that register
2
C register read/write access to guarantee that
2
C bus activity. In addition, a
2
C interface.
Figure 17-11
I
2
C Interfaces
17-19
is