MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 1199

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

A
Address broadcast enable, 7-23
Address mask (LBC), 10-11
AFEU
Alignment
Application
Arbiter, see CSB arbiter and bus monitor
Arbitration
Architecture, overview of device, 1-7
Architecture, PowerPC, 7-13
B
Big-endian, 12-3, 12-19, 13-25, 16-7
Block address translation (BAT), 7-3
Block diagrams
Freescale Semiconductor
status register, 14-34, 14-44
overview, 7-32
examples, 1-18
information, see Initialization/application information
I
see also Memory Management Unit (MMU), 7-3
clock subsystem, 4-29
DDR controller, 9-2, 9-29
DMA/messaging unit, 12-1
DUART, 18-2
e300 core, 1-9
eTSEC, 15-2
general purpose timers, 5-49
GPIOn module, 21-1
I/O sequencer, 11-1
I
IPIC interupt sources, 8-3
JTAG interface, 20-1
local bus controller (LBC), 10-1
PCI, 13-1
periodic interval timer, 5-43, 5-47
real time clock module, 5-36, 5-41
security engine, 1-10
SPI, 19-2
timer pair-cascaded mode, 5-63
2
2
C interface
C interface, 17-1
arbitration control, 17-13
loss of arbitration—forcing of slave mode, 17-23
procedure for arbitration, 17-13
DMA controller, 12-16
MPC8313E PowerQUICC™ II Pro Integrated Processor Reference Manual, Rev. 2
Index
Boot sequencer
Boundary-scan testing, see JTAG interface
Branch processing unit (BPU), 7-1
Branch trace enable (BE), 7-18
Breakpoints
Buffer descriptors, see eTSEC, buffer descriptors
Bus interface
Bus interface unit (BIU), 7-10
Bus monitor, see CSB arbiter and bus monitor
C
Caches
Channel reset, 14-64
cint (critical interrupt signal), 8-2
Clock multiplier, 7-12
Clocks
timers super-cascaded mode, 5-63
watchdog timer, 5-29, 5-34
I
overview, 7-7
signaling, 7-38
I
PCI bus arbitration unit, 1-13
cache locking
operations, 7-10
way-locking, 7-30
DDR clock distribution, 9-42
eTSEC
I
introduction, 4-28
LBC bus clocks and clock ratios, 10-3
PCI agent mode, 4-30
PCI host mode, 4-30
signals, 4-3–4-4
2
2
2
C interface, 4-23–4-25, 17-2, 17-15
C, 1-16
C
way locking, 7-30
inputs and outputs, 15-8
management clock out (EC_MDC), 15-9, 15-73
clock stretching, 17-15
clock synchronization, 17-15
input synchronization and digital filter, 17-15
clock ratio register (LCRR), 10-33
PCI clock outputs (PCI_CLK_OUT[0:7]), 4-30
PCI_CLK, 4-4
PCI_CLK_OUT[0:7], 4-4, 4-30
Index-1