MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 274

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

System Configuration
5.8.1
Table 5-65
5.8.2
Table 5-66
5-66
PMC_PWR_
EXT_PWR_
QUIESCE
0x00B14–
Signal
0x00B0C
0x00BFC
0x00B00
0x00B04
0x00B08
0x00B10
CTRL
Offset
OK
describes the power management signals.
shows the memory map for the power management controller registers.
External Signal Description
PMC Memory Map/Register Definition
I/O
O
O
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
I
Power management controller configuration register (PMCCR)
Power management controller event register (PMCER)
Power management controller mask register (PMCMR)
Power management controller configuration register 1 (PMCCR1)
Power management controller configuration register 2 (PMCCR2)
Reserved
Quiesce state. Indicates that the processor system and PowerPC core are in low power state.
External power control. Enables the external switch to provide power to the device.
Stable power. Indicates whether the power supply on the board is stable.
Meaning
Meaning
Meaning
Timing The timing between a quiesce request from the PowerPC core and the assertion of the external
Timing —
Timing —
Table 5-65. System Control Signals—Detailed Signal Descriptions
Table 5-66. Power Management Controller Registers Memory Map
State
State
State
Asserted—The system and PowerPC core are in low power state.
Negated—The system and PowerPC core are not in low power state.
indication or between negation of the core’s quiesce request and negation of the external
indication depends on the current state of the internal system units and may vary accordingly.
Asserted—Power is supplied to the switchable power supply.
Negated—Power is removed from the switchable power supply.
Asserted—The external power supply is stable to specifications.
Negated—The external power supply is off or not stable to specifications.
Register
Description
Access
R/W
R/W
R/W
R/W
R/W
—
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0002_0002
Reset
—
Freescale Semiconductor
Section/Page
5.8.2.1/5-67
5.8.2.2/5-68
5.8.2.3/5-70
5.8.2.4/5-70
5.8.2.5/5-72
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