MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 897

Manufacturer Part Number

MPC8313ECZQADDC

Microprocessors - MPU 8313 REV2.2 PB ENC EXT

Manufacturer

Freescale Semiconductor

Processor Series

Data Bus Width

Maximum Clock Frequency

Program Memory Size

Data Ram Size

Interface Type

Mounting Style

Package / Case

Number Of Programmable I/os

Number Of Timers

The 1588 timer module can be partitioned into four different sub-modules as shown in

Every incoming packet’s 8-byte timestamp is inserted into the packet data buffer as padding alignment

bytes. Timestamp insertion into the data buffer requires RCTRL[PAL] to be set to a value greater than or

equal to 8 and the control bit RCTRL[TS] bit to be set.

The required timestamp point, as specified in the IEEE 1588 Specification Sep-2004 (IEC 61588 First

Edition), is shown in Figure 15-140. From this, it is clear that the end of the SFD is the critical point in the

MII data stream.

Freescale Semiconductor

Recognition of incoming PTP packet through filer rule match

Phase aligned adjustable (divide by N) clock output

Supports all Ethernet modes supported by the eTSEC, including full- and half-duplex modes

Supports both master and slave modes

Supports timestamp of nano-second resolution

Timer Logic Overview

Timestamp Insertion on the Received Packets

MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2

Timestamp Point

Figure 15-139. 1588 Timer Design Partition

SFD Detection

Enhanced Three-Speed Ethernet Controllers

Ethernet MAC