MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 315

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

See
ACR[RPTCNT]PCI.
6.3.1.3
The ARTRY protocol is used primarily by the CPU to interrupt a transaction that hits to a modified line in
its D-cache, so that it can maintain data coherency by performing the snoop copyback. When CPU asserts
ARTRY, the bus is immediately granted to the CPU to perform snoop copyback. After the completion of
snoop copyback, the arbiter grants the bus back to the master that had its transaction ARTRYed.
6.3.1.4
The arbiter supports address bus parking. This feature implies that when no master is requesting the bus
(all bus requests are negated), the arbiter can choose to park the address bus (or assert the address bus
grant) to a master. The parked master can skip the bus request and assume the bus mastership directly. This
reduces the access latency for parked master.
See
ACR[PARKM].
6.3.1.5
For every committed address tenure a data tenure is required to complete the transaction.
In the device system, the arbiter controls the issuing of data bus grants to a master and a slave, which are
involved in a data tenure of a previously performed address tenure.
6.3.2
The arbiter is responsible for tracking the following cases on the bus:
6.3.2.1
Address time out occurs, if the address tenure was not ended before the specified time-out period
(programmed by ATR[ATO]). In this case, the arbiter performs as follows:
Freescale Semiconductor
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1. Ends the address tenure.
2. Starts data tenure and ends it by asserting transfer error.
3. Reports on the event to AER[ATO].
Section 6.2.1, “Arbiter Configuration Register (ACR),”
Section 6.2.1, “Arbiter Configuration Register (ACR),”
Address time out
Data time out
Transfer error
Address only transaction type
Reserved transaction type
Illegal (eciwx/ecowx) transaction type
Bus Error Detection
Address Bus Arbitration after ARTRY
Address Bus Parking
Data Bus Arbitration
Address Time Out
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
for more details about programming
for more details about ACR[APARK] and
Arbiter and Bus Monitor
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