MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 277

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
Bits
26
27
28
29
30
31
eTSEC1 Wake-up event detected.
eTSEC2 Wake-up event detected.
TIMER
Name
PMCI
INT1
INT2
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
0 A wake-up event did not occur from this wake-up source.
1 A wake-up event occurred on eTSEC1. This wake-up event was caused by a detection of a Magic Packet
Note: This bit will not be affected by the wake-up event if the corresponding mask bit in PMCMR is cleared.
0 A wake-up event did not occur from this wake-up source.
1 A wake-up event occurred on eTSEC2. This wake-up event was caused by a detection of a Magic Packet
Note: This bit will not be affected by the wake-up event if the corresponding mask bit in PMCMR is cleared.
Wake-up event detected.
0 A wake-up event did not occur from this wake-up source.
1 A wake-up event occurred on General Purpose Timer 1. This wake up event was caused by a detection
Note: This bit will not be affected by the wake-up event if the corresponding mask bit in PMCMR is cleared.
Wake-up event detected.
0 A wake-up event did not occur from this wake-up source.
1 A wake-up event occurred on external interrupt request 1. This wake-up event was caused by a detection
Note: This bit will not be affected by the wake-up event if the corresponding mask bit in PMCMR is cleared.
Wake-up event detected.
0 A wake-up event did not occur from this wake-up source.
1 A wake-up event occurred on external interrupt request 2. This wake-up event was caused by a detection
Note: This bit will not be affected by the wake-up event if the corresponding mask bit in PMCMR is cleared.
Power management controller interrupt.
When set, indicates that one of the following events has occurred:
If PMCMR[PMCIE] is set, the PMC interrupt request to the PowerPC core is driven, causing the PowerPC
core to exit its low power state. PMCI can be cleared by writing a 1 to it (writing zero has no effect).
• One of the unmasked wake-up events (bits 23–30) occurred and PMCCR1[PME_vPEN] is cleared, or
• PM current state (as indicated in PMCCR1[CURR_STATE]) is different than PM next state (as written to
• CSB platform is in low power mode and a new CSB bus request is detected
on the receive path of eTSEC1.
details. I If the corresponding PMCMR bit is set, the PMC will assert interrupt request to the PowerPC
core or external PME to the remote host, depending on the state of PMCCR1[PME_EN]. This bit can be
cleared by writing a 1 to the bit location (writing zero has no effect).
on the receive path of eTSEC2. See
more details. I If the corresponding PMCMR bit is set, the PMC will assert interrupt request to the
PowerPC core or external PME to the remote host, depending on the state of PMCCR1[PME_EN]. This
bit can be cleared by writing a 1 to the bit location (writing zero has no effect).
of match between timer current value and timer reference value of the fourth 16 bit unit of GTM1. See
Section 5.7, “General-Purpose Timers
the PMC will assert interrupt request to the PowerPC core or external PME to the remote host,
depending on the state of PMCCR1[PME_EN]. This bit can be cleared by writing a 1 to the bit location
(writing zero has no effect).
of an active state of the IRQ1 external pin. If the corresponding PMCMR bit is set, the PMC will assert
interrupt request to the PowerPC core or external PME to the remote host, depending on the state of
PMCCR1[PME_EN]. This bit can be cleared by writing a 1 to the bit location (writing zero has no effect).
of an active state of the IRQ2 external pin. If the corresponding PMCMR bit is set, the PMC will assert
interrupt request to the PowerPC core or external PME to the remote host, depending on the state of
PMCCR1[PME_EN]. This bit can be cleared by writing a 1 to the bit location (writing zero has no effect).
PCIPMR1[Power_State] and indicated in PMCCR1[NEXT_STATE]) and PMCCR1[USE_STATE] is set,
or
Table 5-68. PMCER Bit Settings (continued)
SeeChapter 15, “Enhanced Three-Speed Ethernet Controllers,”
Chapter 15, “Enhanced Three-Speed Ethernet Controllers,”
(GTMs),”for more details. If the corresponding PMCMR bit is set,
Description
System Configuration
for more
for
5-69