MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 781

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 15-23
15.5.3.3.12 Receive Descriptor Base Address Registers (RBASE0–RBASE7)
The RBASEn registers are written by the user with the base address of each RxBD ring n. Each such value
must be divisible by eight, since the 3 least-significant bits always write as 000.
RBASEn registers.
Table 15-24
15.5.3.3.13 Receive Stamp Register (TMR_RXTS_H/L)
Receive timestamp register (RXTS_H/L). This register holds the value present in TMR_CNT_H/L when
the eTSEC detects a new incoming Ethernet frame. This register is only updated when the precision
timestamp logic is enable via TMR_CTRL[TE]. This register is read only in normal operation. Figure
15-35 describes the definition for the RXTS_H/L register.
Freescale Semiconductor
29–31
29–31
0–28
0–28
Bits
Bits
Offset eTSEC1:0x2_4404+8× n ; eTSEC2:0x2_5404+8× n
Reset
W
R
RBASE n Receive base for ring n . RBASE defines the starting location in the memory map for the eTSEC RxBDs.
RBPTR n
Name
0
Name
—
—
describes the fields of the RBPTRn register.
describes the fields of the RBASEn registers.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
This field must be 8-byte aligned. Together with setting the W (wrap) bit in the last BD, the user can select
how many BDs to allocate for the receive packets. The user must initialize RBASE before enabling the
eTSEC receive function on the associated ring.
Reserved
Current RxBD pointer for RxBD ring n . Points to the current BD being processed or to the next BD the
receiver uses when it is idling. After reset or when the end of the RxBD ring is reached,
eTSEC initializes RBPTR n to the value in the corresponding RBASE n . The RBPTR register is internally
written by the eTSEC’s DMA controller during reception. The pointer increments by 8 (bytes) each time a
descriptor is closed successfully by the eTSEC. Note that the 3 least-significant bits of this register are
read only and zero.
Reserved
Table 15-38. RBASE0–RBASE7 Field Descriptions
Figure 15-34. RBASE Register Definition
Table 15-37. RBPTR n Field Descriptions
RBASE n
All zeros
Description
Description
Enhanced Three-Speed Ethernet Controllers
Figure 15-34
Access: Read/Write
describes the
28 29
—
15-63
31