MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 1119

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Figure 18-8
Table 18-12
18.3.1.7
The ULCRs specify the data format for the UART bus and set the divisor latch access bit ULCR[DLAB],
which controls the ability to access the divisor latch least and most significant bit registers and the alternate
function register.
After initializing ULCR, the software should not rewrite the ULCR while valid transfers on the UART bus
are active. The software should not rewrite the ULCR until the last STOP bit is received and no new
characters are being transferred on the bus.
The stick parity bit, ULCR[SP], assigns a set parity value for the parity bit time slot sent on the UART bus.
The set value is defined as mark parity (logic 1) or space parity (logic 0). ULCR[PEN] and ULCR[EPS]
help determine the set parity value. See
be sent at the end of the data transfer. The receiver checks only the first STOP bit, regardless of the number
Freescale Semiconductor
Bits
0–1
2–3
4
5
6
7
Name
DMS
RFR
TFR
FEN
RTL
Offset: 0x0_4502, 0x0_4602
—
Reset
shows the bits in the UFCRs.
describes the fields of the UFCRs.
Line Control Registers (ULCR1 and ULCR2)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
W
R
Receiver trigger level. A received data available interrupt occurs when UIER[ERDAI] is set and the number
of bytes in the receiver FIFO equals RTL value.
00 1 byte
01 4 bytes
10 8 bytes
11 14 bytes
Reserved
DMA mode select. See
0 UDSR[RXRDY] and UDSR[TXRDY] bits are in mode 0.
1 UDSR[RXRDY] and UDSR[TXRDY] bits are in mode 1 if UFCR[FEN] = 1.
Transmitter FIFO reset
0 No action
1 Clears all bytes in the transmitter FIFO and resets the FIFO counter/pointer to 0
Receiver FIFO reset
0 No action
1 Clears all bytes in the receiver FIFO and resets the FIFO counter/pointer to 0
FIFO enable
0 FIFOs are disabled and cleared
1 Transmitter and receiver FIFOs are enabled.
0
RTL
Figure 18-8. FIFO Control Registers (UFCR1 and UFCR2)
1
Table 18-12. UFCR Field Descriptions
Section 18.4.5.2, “DMA Mode Select”
Table
2
—
18-14. ULCR[NSTB] defines the number of STOP bits to
3
All zeros
Description
DMS
4
TFR
5
Access: User write-only
RFR
6
FEN
7
DUART
18-11