MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 790

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
15.5.3.5.5
The MAXFRM register is written by the user.
Table 15-44
15.5.3.5.6
The MIIMCFG register is written by the user to configure all MII management operations. Note that MII
management hardware is shared by all eTSECs. Thus, only through the MIIM registers of eTSEC1 can
external PHYs be accessed and configured. Note: when an eTSEC is configured to use RTBI,
configuration of the RTBI (described in
15-72
16–19
20–25
26–31
16–31 Maximum Frame By default this field is set to 0x0600 (1536 bytes). It sets the maximum Ethernet frame size in both
0–15
Bits
Bits
14
15
Offset
Reset 0
W
R
Collision Window This is a programmable field representing the slot time or collision window during which collisions
Retransmission
0
Excess Defer
eTSEC1:0x2_4510; eTSEC2:0x2_5510
No BackOff
Maximum
Name
0
describes the fields of the MAXFRM register.
Name
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
—
—
Maximum Frame Length Register (MAXFRM)
MII Management Configuration Register (MIIMCFG)
0
0
0
Reserved
the transmit and receive directions. (Refer to MACCFG2[Huge Frame].)
Note that if MACCFG2[Huge Frame] = 0, the value of this field must be less than or equal to
MRBLR[MRBL] × (minimum number of RxBDs per ring). See
Configuration 2 Register
Register
Figure 15-40. Maximum Frame Length Register Definition
No backoff. This bit is cleared by default.
0 The Tx MAC follows the binary exponential back off rule.
1 The Tx MAC immediately re-transmits following a collision.
Excessively deferred. This bit is set by default.
0 The Tx MAC aborts the transmission of a packet that is excessively deferred.
1 The Tx MAC allows the transmission of a packet that is excessively deferred.
This is a programmable field specifying the number of retransmission attempts following a collision
before aborting the packet due to excessive collisions. The standard specifies the attempt limit to
be 0xF (15d). Its default value is 0xF.
Reserved
occur in properly configured networks. Because the collision window starts at the beginning of
transmission, the preamble and SFD are included. Its default of 0x37 (55d) corresponds to the
count of frame bytes at the end of the window.
0
Table 15-43. HAFDUP Field Descriptions (continued)
0
(MRBLR),” and
0
—
0
Table 15-44. MAXFRM Descriptions
0
0
Section 15.5.4, “Ten-Bit Interface
0
Section 15.6.7.3, “Receive Buffer Descriptors
(MACCFG2),”
0
Figure 15-40
0
0
15 16
0
Section 15.5.3.3.9, “Maximum Receive Buffer Length
0
Description
Description
shows the MAXFRM register.
0
0
0
0
1
Section 15.5.3.5.2, “MAC
Maximum Frame
(TBI)”) is done through the
1
0
(RxBD).”
0
Freescale Semiconductor
0
0
Access: Read/Write
0
0
0
0
31
0