MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 31

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Paragraph
Number
16.6
16.6.1
16.6.2
16.6.3
16.6.4
16.6.4.1
16.6.5
16.6.6
16.6.7
16.6.8
16.6.8.1
16.6.8.2
16.6.8.2.1
16.6.9
16.6.9.1
16.6.9.2
16.6.9.3
16.6.9.4
16.6.9.5
16.6.10
16.6.10.1
16.6.10.2
16.6.10.3
16.6.11
16.6.12
16.6.12.1
16.6.12.1.1
16.6.12.1.2
16.6.12.2
16.6.12.2.1
16.6.12.2.2
16.6.12.2.3
16.6.12.2.4
16.6.12.2.5
16.6.12.2.6
16.6.12.2.7
16.6.12.2.8
16.6.12.2.9
16.6.12.3
16.6.12.3.1
16.6.12.3.2
Freescale Semiconductor
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Host Operations ........................................................................................................... 16-67
Host Controller Initialization ................................................................................... 16-68
Power Port................................................................................................................ 16-69
Reporting Over-Current ........................................................................................... 16-69
Suspend/Resume...................................................................................................... 16-69
Schedule Traversal Rules......................................................................................... 16-71
Periodic Schedule Frame Boundaries vs. Bus Frame Boundaries........................... 16-72
Periodic Schedule .................................................................................................... 16-75
Managing Isochronous Transfers Using iTDs ......................................................... 16-76
Asynchronous Schedule........................................................................................... 16-80
Managing Control/Bulk/Interrupt Transfers via Queue Heads................................ 16-85
Ping Control............................................................................................................. 16-89
Split Transactions..................................................................................................... 16-90
Port Suspend/Resume .......................................................................................... 16-70
Host Controller Operational Model for iTDs ...................................................... 16-76
Software Operational Model for iTDs ................................................................. 16-78
Adding Queue Heads to Asynchronous Schedule ............................................... 16-81
Removing Queue Heads from Asynchronous Schedule...................................... 16-82
Empty Asynchronous Schedule Detection .......................................................... 16-84
Asynchronous Schedule Traversal: Start Event................................................... 16-85
Reclamation Status Bit (USBSTS Register)........................................................ 16-85
Buffer Pointer List Use for Data Streaming with qTDs ...................................... 16-86
Adding Interrupt Queue Heads to the Periodic Schedule.................................... 16-88
Managing Transfer Complete Interrupts from Queue Heads .............................. 16-88
Split Transactions for Asynchronous Transfers................................................... 16-90
Split Transaction Interrupt ................................................................................... 16-92
Split Transaction Isochronous ........................................................................... 16-104
Periodic Scheduling Threshold........................................................................ 16-79
Asynchronous—Do-Start-Split........................................................................ 16-91
Asynchronous—Do-Complete-Split ............................................................... 16-91
Split Transaction Scheduling Mechanisms for Interrupt ................................. 16-92
Host Controller Operational Model for FSTNs ............................................... 16-95
Software Operational Model for FSTNs ......................................................... 16-97
Tracking Split Transaction Progress for Interrupt Transfers ........................... 16-98
Split Transaction Execution State Machine for Interrupt ................................ 16-98
Periodic Interrupt—Do-Start-Split .................................................................. 16-99
Periodic Interrupt—Do-Complete-Split ........................................................ 16-100
Managing the QH[FrameTag] Field .............................................................. 16-103
Rebalancing the Periodic Schedule ............................................................... 16-104
Split Transaction Scheduling Mechanisms for Isochronous ......................... 16-105
Tracking Split Transaction Progress for Isochronous Transfers.................... 16-108
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